Ring isolated through-substrate vias for high resistivity substrates

• US 10,643,927 B1
• Filed: 11/16/2018
• Issued: 05/05/2020
• Est. Priority Date: 11/16/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Shank, Steven, McCallum-Cook, Ian, Hall, John
• Primary Examiner(s): Chang, Jay C
• Application Number:
  US16/192,999
• Publication Number:
  US 20200161218A1
• Time in Patent Office: 536 Days
• Field of Search: None
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

Through-substrate vias (TSVs) extend through a high resistivity semiconductor substrate laterally spaced and isolated from an active device formed over the substrate by deep trench isolation (DTI) structures. The deep trench isolation structures may extend partially or entirely through the substrate, and may include an air gap. The deep trench isolation structures entirely surround the active device and the TSVs.

Claims

1. A semiconductor chip comprising:

a high resistivity semiconductor substrate;

an electronic device formed over a front side of the substrate;

a through-substrate via laterally spaced from the electronic device;

a first deep trench isolation structure extending at least partially through the substrate and laterally spaced from and surrounding the electronic device; and

a second deep trench isolation structure extending at least partially through the substrate and laterally spaced from and surrounding the through-substrate via,

wherein a portion of the first deep trench isolation structure is contiguous with a portion of the second deep trench isolation structure.

2. The semiconductor chip of claim 1, wherein the high resistivity semiconductor substrate has a bulk resistivity of greater than 1000 ohm-cm.

3. The semiconductor chip of claim 1, further comprising an air gap independently within each of the first deep trench isolation structure and the second deep trench isolation structure.

4. The semiconductor chip of claim 3, wherein the air gap within each of the first deep trench isolation structure and the second deep trench isolation structure independently extends above a top surface of the substrate.

5. The semiconductor chip of claim 1, wherein the first deep trench isolation structure and the second deep trench isolation structure independently extend vertically entirely through the substrate.

6. The semiconductor chip of claim 1, further comprising a metallization layer disposed over a back side of the substrate.

7. The semiconductor chip of claim 6, wherein the through-substrate via is metalized and the metallization layer is in electrical contact with the metalized through-substrate via.

8. The semiconductor chip of claim 6, further comprising a passivation layer disposed over the back side of the substrate, where the metallization layer is disposed over the passivation layer.

9. The semiconductor chip of claim 8, wherein the passivation layer is in direct contact with the first deep trench isolation structure and the second deep trench isolation structure.

10. The semiconductor chip of claim 1, wherein a distance between the electronic device and the through-substrate via is less than 25 microns.

11. The semiconductor chip of claim 1, further comprising a shallow trench isolation layer disposed between the first deep trench isolation layer and the electronic device and laterally adjacent to and surrounding the electronic device.

12. A semiconductor chip comprising:

a high resistivity semiconductor substrate;

an electronic device formed over a front side of the substrate;

a metallization layer disposed over a back side of the substrate;

a through-substrate via laterally spaced from the electronic device;

a first deep trench isolation structure extending at least partially through the substrate and laterally spaced from and surrounding the electronic device;

a second deep trench isolation structure extending at least partially through the substrate and laterally spaced from and surrounding the through-substrate via; and

a first air gap independently within the first deep trench isolation structure and a second air gap independently within the second deep trench isolation structure,

wherein a portion of the first deep trench isolation structure is contiguous with a portion of the second deep trench isolation structure.

13. The semiconductor chip of claim 12, wherein the high resistivity semiconductor substrate has a bulk resistivity of greater than 1000 ohm-cm.

14. The semiconductor chip of claim 12, wherein the first air gap within the first deep trench isolation structure and the second air gap within the second deep trench isolation structure independently extend above a top surface of the substrate.

15. The semiconductor chip of claim 12, wherein the first deep trench isolation structure and the second deep trench isolation structure independently extend vertically entirely through the substrate.

16. The semiconductor chip of claim 12, further comprising a passivation layer disposed over the back side of the substrate, where the metallization layer is disposed over the passivation layer, wherein the passivation layer is in direct contact with the first deep trench isolation structure and the second deep trench isolation structure.

17. The semiconductor chip of claim 12, wherein a distance between the electronic device and the through-substrate via is less than 25 microns.

18. The semiconductor chip of claim 12, further comprising a shallow trench isolation layer disposed between the first deep trench isolation layer and the electronic device and laterally adjacent to and surrounding the electronic device.

19. A semiconductor chip comprising:

a high resistivity semiconductor substrate;

an electronic device formed over a front side of the substrate;

a through-substrate via laterally spaced from the electronic device;

a first deep trench isolation structure extending at least partially through the substrate and laterally spaced from and surrounding the electronic device; and

a second deep trench isolation structure extending at least partially through the substrate and laterally spaced from and surrounding the through-substrate via,

wherein the first deep trench isolation structure and the second deep trench isolation structure independently extend vertically entirely through the substrate.