Semiconductor device with semiconductor chips of different sizes and manufacturing method threreof

• US 10,643,930 B2
• Filed: 11/30/2017
• Issued: 05/05/2020
• Est. Priority Date: 12/28/2016
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Danno, Tadatoshi, Nishikizawa, Atsushi, Nakamura, Hiroyuki
• Primary Examiner(s): Ahmadi, Mohsen
• Application Number:
  US15/826,815
• Publication Number:
  US 20180182692A1
• Time in Patent Office: 887 Days
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/4828 Etching etching for cleaning without patterning H01L21/4835
• CPC Class Codes: H01L 21/4842 Mechanical treatment, e.g. punching, cutting, deforming, cold welding
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/495 Lead-frames or other flat leads H01L23/498 takes precedence; lead frame interconnections between components H01L23/52
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49531 the additional leads being a wiring board
• CPC Class Codes: H01L 23/49551 characterised by bent parts
• CPC Class Codes: H01L 23/49568 specifically adapted to facilitate heat dissipation
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49582 Metallic layers on lead frames
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H02P 27/06 : using dc to ac converters or inverters H02P27/05 takes precedence

Abstract

An improvement is achieved in the reliability of a semiconductor device. A SIP includes an analog chip, a microcomputer chip having a main surface smaller in area than a main surface of the analog chip, a die pad over which the analog chip and the microcomputer chip are mounted, and a plurality of leads arranged so as to surround the die pad. The SIP further includes a plurality of suspension leads formed integrally with the die pad, a plurality of wires electrically coupling electrodes of the analog chip to the leads and electrically coupling the microcomputer chip to the leads, and a sealing body sealing therein the analog chip and the microcomputer chip. Each of first and second curved portions of the die pad has a radius of curvature larger than a radius of curvature of a third curved portion of the die pad.

Claims

1. A semiconductor device, comprising:

a first semiconductor chip having a first main surface over which a plurality of first electrodes and a plurality of second electrodes are formed;

a second semiconductor chip having a second main surface over which a plurality of third electrodes and a plurality of fourth electrodes are formed;

a chip mounting portion having a third main surface over which the first and second semiconductor chips are mounted;

a plurality of leads arranged so as to surround the chip mounting portion;

a plurality of suspension leads formed integrally with the chip mounting portion;

a plurality of first conductive members electrically connecting the plurality of first electrodes with a plurality of first leads which are included in the plurality of leads;

a plurality of second conductive members electrically connecting the third electrodes with a plurality of second leads which are included in the plurality of leads; and

a sealing body sealing the first semiconductor chip, the second semiconductor chip, a portion of the chip mounting portion, a portion of each of the plurality of leads, the plurality of first conductive members, and the plurality of second conductive members,

wherein, in plan view, a size of the first main surface of the first semiconductor chip is larger than a size of the second main surface of the second semiconductor chip,

wherein, in plan view, the first semiconductor chip has a first side extending in a first direction, and a second side extending in a second direction crossing the first direction,

wherein, in plan view, the second semiconductor chip has a third side extending in the first direction and a fourth side extending in the second direction,

wherein, in plan view, the first side of the first semiconductor chip and the third side of the second semiconductor chip are located between the second side of the first semiconductor chip and the fourth side of the second semiconductor chip,

wherein, in plan view, the chip mounting portion has a fifth side extending along and adjacent to the first side, a sixth side extending along and adjacent to the second side, a seventh side extending along and adjacent to the third side, an eighth side extending along and adjacent to the fourth side, and a ninth side located between the fifth and seventh sides and extending along the second direction,

wherein, in plan view, the chip mounting portion has a first curved portion continued to each of the fifth and ninth sides and a second curved portion continued to each of the seventh and eighth sides,

wherein, in plan view, the sealing body has a plurality of outside corner portions,

wherein a first suspension lead which is included in the plurality of suspension leads extends from the seventh side toward a first outside corner portion which is among the plurality of outside corner portions of the sealing body, the first outside corner portion being located closest to the seventh side among the plurality of outside corner portions,

wherein a second suspension lead which is included in the plurality of suspension leads extends from a corner portion defined by the fifth and sixth sides toward a second outside corner portion which is among in the plurality of outside corner portions of the sealing body,

wherein, in plan view, the second suspension lead has a tenth side extending from the chip mounting portion toward the second outside corner portion,

wherein, in plan view, the chip mounting portion has a third curved portion continued to each of the tenth and fifth sides,

wherein each of the first and second curved portions has a radius of curvature larger than a radius of curvature of the third curved portion,

wherein the third main surface of the chip mounting portion has;

a first portion over which the first semiconductor chip is mounted and having the fifth side and the sixth side; and

a second portion over which the second semiconductor chip is mounted and having the seventh side and the eighth side,

wherein, in plan view, a size of the third main surface in the second portion is smaller than a size of the third main surface in the first portion, and

wherein a length of the eighth side is shorter than a length of the sixth side.

2. The semiconductor device according to claim 1,

wherein the chip mounting portion has a back surface opposite to the third main surface and exposed from the sealing body.

3. The semiconductor device according to claim 1, wherein

the plurality of second electrodes of the first semiconductor chip is electrically connected with the fourth electrodes of the second semiconductor chip via a plurality of third conductive members.

4. The semiconductor device according to claim 1,

wherein each of the plurality of leads has an end portion extending toward the chip mounting portion, and

wherein a silver plating film is formed over the end portion.

5. The semiconductor device according to claim 1,

wherein, in plan view, a plurality of protruding portions is formed on each of side surfaces of the chip mounting portion which respectively correspond to the fifth, sixth, seventh, and eighth sides thereof, and

wherein each of the protruding portions is bent toward the first and second semiconductor chips.

6. The semiconductor device according to claim 1,

wherein each of the plurality of leads, the plurality of suspension leads, and the chip mounting portion contains copper as a main component, and

wherein the third main surface of the chip mounting portion has a planarity lower than a planarity of a first back surface of the first semiconductor chip which is opposite to the first main surface thereof.

7. The semiconductor device according to claim 1,

wherein the plurality of leads disposed in a region between the first and second suspension leads includes a lead having a respective tip portion located on one side of the fifth side of the chip mounting portion in the second direction in plan view and a lead having a respective tip portion located on a side opposite to the one side of the fifth side of the chip mounting portion in the second direction in plan view.

8. The semiconductor device according to claim 1,

wherein an area of the third main surface of the chip mounting portion is larger than a sum of an area of the first main surface of the first semiconductor chip and an area of the second main surface of the second semiconductor chip.