Electronic device with die being sunk in substrate

• US 10,643,940 B2
• Filed: 01/11/2019
• Issued: 05/05/2020
• Est. Priority Date: 06/17/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Fontana, Fulvio Vittorio, Graziosi, Giovanni
• Primary Examiner(s): Wright, Tucker J
• Assistant Examiner(s): Baptiste, Wilner Jean
• Application Number:
  US16/245,549
• Publication Number:
  US 20190148282A1
• Time in Patent Office: 480 Days
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/52 Mounting semiconductor bodies in containers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

Claims

1. A method for manufacturing an electronic device, comprising:

mounting a back surface of a die to a mounting surface of a cap, said die including an integrated circuit, a front surface opposite the back surface, and one or more die terminals on the front surface for accessing the integrated circuit;

providing a package substrate having a package front surface and a package back surface opposed to each other and a through-hole crossing the package substrate between the package front surface and the package back surface;

mounting the package back surface of the package substrate to the cap with the die positioned within the through-hole crossing the package substrate;

applying a first insulating layer of electrically insulating material onto the package front surface and the front surface of the die;

opening one or more first windows in the first insulating layer with each first window accessing a corresponding one of the die terminals;

forming one or more package terminals and one or more package tracks of electrically conductive material onto the first insulating layer, each package track electrically coupling a corresponding one of the package terminals with at least a corresponding one of the die terminals; and

applying a second insulating layer of electrically insulating material onto the first insulating layer and the package tracks, the second insulating layer having one or more second windows with each second window accessing a corresponding one of the package terminals.

2. The method of claim 1, wherein the first insulating layer comprises a B-stageable adhesive.

3. The method of claim 1, further comprising curing the first insulating layer to attach the front surface of the die to the first insulating layer.

4. The method of claim 1, further comprising depositing a thermally conductive material into a gap between peripheral surfaces of the die and the package substrate.

5. The method of claim 4, wherein the thermally conductive material is silicone.

6. The method of claim 1, wherein applying the second insulating layer comprises solder mask screening.

7. The method of claim 1, further comprising positioning the die within the through-hole such that said die front surface and die back surface are coplanar to the package front surface and to the package back surface, respectively.

8. A method for manufacturing an electronic device, comprising:

providing a package substrate having a package front surface and a package back surface opposed to each other, and at least one through-hole crossing the package substrate between the package front surface and the package back surface;

attaching a die to a cap, said die including an integrated circuit, a die front surface and a die back surface opposed to each other, and one or more die terminals on the die front surface for accessing the integrated circuit;

mounting the package substrate to the cap with the die positioned within the through-hole in a position where the die front surface is coplanar to the package front surface;

applying a first insulating layer of electrically insulating material onto the package front surface and die front surface;

opening one or more first windows in the first insulating layer with each first window accessing a corresponding one of the die terminals;

forming one or more package terminals and one or more package tracks of electrically conductive material onto the first insulating layer, each package track electrically coupling a corresponding one of the package terminals with at least a corresponding one of the die terminals; and

applying a second insulating layer of electrically insulating material onto the first insulating layer and the package tracks, the second insulating layer having one or more second windows with each second window accessing a corresponding one of the package terminals.

9. The method of claim 8, further comprising depositing a thermally conductive material into a gap between peripheral surfaces of the die and the package substrate.

10. The method of claim 9, wherein the deposited thermally conductive material is silicone.

11. A method for manufacturing an electronic device, comprising:

providing a package substrate having a package front surface and a package back surface opposed to each other and at least one through-hole crossing the package substrate between the package front surface and the package back surface;

inserting a die within the through-hole, said die including an integrated circuit, a die front surface and a die back surface opposed to each other, and one or more die terminals on the die front surface for accessing the integrated circuit, said die terminals facing the first insulating layer;

applying a first insulating layer of electrically insulating material onto the package front surface and die front surface;

opening one or more first windows in the first insulating layer with each first window accessing a corresponding one of the die terminals;

forming one or more package terminals and one or more package tracks of electrically conductive material onto the first insulating layer, each package track electrically coupling a corresponding one of the package terminals with at least a corresponding one of the die terminals; and

applying a second insulating layer of electrically insulating material onto the first insulating layer and the package tracks, the second insulating layer having one or more second windows with each second window accessing a corresponding one of the package terminals.

12. The method of claim 11, further comprising mounting a cap to the die back surface.

13. The method of claim 12, further comprising mounting the cap to the package back surface.

14. The method of claim 11, wherein the first insulating layer comprises a B-stageable adhesive.

15. The method of claim 11, further comprising depositing a thermally conductive material into a gap between peripheral sidewalls of the integrated circuit die and the package substrate.

16. The method of claim 15, wherein the thermally conductive material is silicone.