Formation of fine pitch traces using ultra-thin PAA modified fully additive process

• US 10,643,942 B2
• Filed: 09/19/2019
• Issued: 05/05/2020
• Est. Priority Date: 02/02/2018
• Status: Active Grant

• Current Assignee: Xiamen Compass Semiconductor Company Limited
• Original Assignee: Compass Technology Company, Limited
• Inventors: Pun, Kelvin Po Leung, Cheung, Chee Wah
• Primary Examiner(s): Sullivan, Caleen O
• Application Number:
  US16/575,554
• Publication Number:
  US 20200013700A1
• Time in Patent Office: 229 Days
• Field of Search: 257762
• CPC Class Codes: C23C 18/1641 Organic substrates, e.g. resin, plastic
• CPC Class Codes: C23C 18/1651 Two or more layers only obtained by electroless plating
• CPC Class Codes: C23C 18/1653 Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
• CPC Class Codes: C23C 18/1689 After-treatment
• CPC Class Codes: C23C 18/1692 Heat-treatment
• CPC Class Codes: C23C 18/2086 with use of organic or inorganic compounds other than metals, first
• CPC Class Codes: C23C 18/30 Activating or accelerating or sensitising with palladium or other noble metal
• CPC Class Codes: C23C 18/36 using hypophosphites
• CPC Class Codes: C25D 3/38 of copper
• CPC Class Codes: C25D 5/02 Electroplating of selected surface areas
• CPC Class Codes: C25D 5/022 using masking means
• CPC Class Codes: C25D 5/10 Electroplating with more than one layer of the same or of different metals for bearings C25D7/10
• CPC Class Codes: C25D 5/611 Smooth layers
• CPC Class Codes: C25D 5/617 Crystalline layers
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 : the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/26175 : Flow barriers
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48229 : the bond pad protruding from the surface of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81444 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81464 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/81466 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/81473 : Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/85203 : Thermocompression bonding
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85464 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/85466 : Titanium (Ti) as principal constituent
• CPC Class Codes: H01L 2224/85473 : Rhodium (Rh) as principal constituent
• CPC Class Codes: H01L 2224/86203 : Thermo-compression bonding
• CPC Class Codes: H01L 2224/8683 : Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/4985 : Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/49866 : characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/86 : using tape automated bonding [TAB]
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A method to produce a substrate suitable for diffusion bonding is described. A flexible dielectric substrate is provided. An alkaline modification is applied to the dielectric substrate to form a polyamic acid (PAA) anchoring layer on a surface of the dielectric substrate. A Ni—P seed layer is electrolessly plated on the PAA layer. Copper traces are plated within a photoresist pattern on the Ni—P seed layer. A surface finishing layer is electrolytically plated on the copper traces. The photoresist pattern and Ni—P seed layer not covered by the copper traces are removed to complete the substrate suitable for diffusion bonding.

Claims

1. A method of manufacturing a flexible substrate comprising:

providing a flexible dielectric substrate;

applying an alkaline modification to said dielectric substrate to form a polyamic acid (PAA) anchoring layer on a surface of said dielectric substrate;

electrolessly plating a Ni—

P seed layer on said PAA layer;

forming a photoresist pattern on said Ni—

P seed layer;

plating copper traces within said photoresist pattern;

plating a surface finishing layer on said copper traces; and

removing said photoresist pattern and etching away said Ni—

P seed layer not covered by said copper traces to complete said flexible substrate.

2. The method according to claim 1 wherein said dielectric substrate comprises:

any kind of polyimide (PI), including Kapton PI or Upisel PI, or liquid crystal polymer (LCP).

3. The method according to claim 1 wherein said alkaline modification comprises applying a KOH/alkaline base chemical to said dielectric substrate wherein said PAA layer has a thickness of less than 100 nm and preferably less than 10 nm.

4. The method according to claim 1 further comprising depositing a catalyst layer comprising Palladium (Pd) or Nickel (Ni) on said PAA layer by immersion into an ionic metal solution to activate said PAA layer for subsequent electroless Ni—

P seed layer plating.

5. The method according to claim 1 wherein said electrolessly plating said Ni—

P seed layer is an autocatalytic process and wherein said Ni—

P seed layer has a thickness of 0.1 μ

m+/−

10% and a composition of Ni;

96.5˜

97.5 wt % and P;

2.5˜

3.5 wt %.

6. The method according to claim 1 wherein said forming said photoresist pattern comprises:

applying a photoresist on said Ni—

P seed layer; and

exposing and developing said photoresist to form a pattern for fine pitch traces for circuitization.

7. The method according to claim 1 further comprising annealing said substrate after forming said Ni—

P seed layer preferably at 200°

C. for at least ten minutes to at most 2 hours.

8. The method according to claim 1 wherein said plating said copper traces comprises electrolytically plating copper to a thickness of between about 2 to 18 μ

m wherein a ratio of the top to bottom widths of said copper traces is close to 1, wherein an elongation strength of said copper traces is over 15%, wherein a tensile strength of said copper traces is between about 290 and 340 N/mm², and wherein a hardness of said copper traces is 100 in vicker hardness with a purity of more than 99.9%.

9. The method according to claim 1 wherein said surface finishing layer comprises electrolytic Ni/Au, electroless Nickel/Immersion gold (ENIG), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), electrolytic Palladium, electrolytic Titanium, electrolytic Tin, electrolytic Rhodium, Electroless Palladium/Autocatalytic Gold (EPAG), or Immersion Gold/Electroless Palladium/Immersion Gold (IGEPIG).

10. A method of manufacturing a flexible substrate comprising:

providing a flexible dielectric substrate;

laser drilling at least one first via opening all the way through said dielectric substrate;

applying an alkaline modification to said dielectric substrate to form a first polyamic acid (PAA) anchoring layer on top and bottom surfaces of said dielectric substrate;

electrolessly plating a first Ni—

P seed layer on top and bottom of said first PAA layers;

forming a first photoresist pattern on top and bottom of said first Ni—

P seed layers;

plating first copper traces within said first photoresist patterns and through said at least one first via opening;

plating a surface finishing layer on said first copper traces; and

removing said first photoresist patterns and etching away said first Ni—

P seed layers not covered by said first copper traces to complete said flexible substrate.

11. The method according to claim 10 wherein said dielectric substrate comprises:

any kind of polyimide (PI), such as Kapton PI or Upisel PI, and liquid crystal polymer (LCP).

12. The method according to claim 10 wherein said alkaline modification comprises applying a KOH/alkaline base chemical to said dielectric substrate wherein said first PAA layers have a thickness of less than 100 nm and preferably less than 10 nm.

13. The method according to claim 10 further comprising depositing catalyst layers comprising Palladium (Pd) or Nickel (Ni) on said top and bottom PAA layers by immersion into an ionic metal solution to activate said first PAA layers for subsequent electroless Ni—

P seed layer plating.

14. The method according to claim 10 wherein said electrolessly plating said first Ni—

P seed layers is an autocatalytic process and wherein said first Ni—

P seed layers have a thickness of 0.1 μ

m+/−

10% and a composition of Ni;

96.5˜

97.5 wt % and P;

2.5˜

3.5 wt %.

15. The method according to claim 10 further comprising annealing said substrate after forming said first Ni—

P seed layers at 200°

C. for at least 10 minutes to at most 2 hours.

16. The method according to claim 10 wherein said plating said first copper traces comprises electrolytically plating copper to a thickness of between about 2 to 18 μ

m wherein a ratio of the top to bottom widths of said copper traces is close to 1, wherein an elongation strength of said copper traces is over 15%, wherein a tensile strength of said copper traces is between about 290 and 340 N/mm², wherein a hardness of said copper traces is 100 in vicker hardness with a purity of more than 99.9%, and wherein a center to center distance between two adjacent said copper traces is less than 8 μ

m.

17. The method according to claim 10 wherein said surface finishing layer comprises electrolytic Ni/Au, electroless Nickel/Immersion gold (ENIG), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), electrolytic Palladium, electrolytic Titanium, electrolytic Tin, electrolytic Rhodium, Electroless Palladium/Autocatalytic Gold (EPAG), or Immersion Gold/Electroless Palladium/Immersion Gold (IGEPIG).

18. A method of manufacturing a flexible substrate comprising:

providing a flexible dielectric substrate;

laser drilling at least one first via opening all the way through said dielectric substrate;

applying an alkaline modification to said dielectric substrate to form a first polyamic acid (PAA) anchoring layer on top and bottom surfaces of said dielectric substrate;

electrolessly plating a first Ni—

P seed layer on top and bottom of said first PAA layers;

forming a first photoresist pattern on top and bottom of said first Ni—

P seed layers;

plating first copper traces within said first photoresist patterns and through said at least one first via opening;

removing said first photoresist patterns and etching away said first Ni—

P seed layers not covered by said first copper traces;

thereafter laminating a bonding film on top and bottom surfaces of said first copper traces;

laminating a dielectric layer on top and bottom of said bonding films;

laser drilling at least one second via opening all the way through said dielectric layer and said bonding film to contact said first copper traces on top and bottom of said substrate;

thereafter applying an alkaline modification to said dielectric layers to form a second polyamic acid (PAA) anchoring layer on top and bottom surfaces of said dielectric layers and within said at least one second via openings;

electrolessly plating a second Ni—

P seed layer on top and bottom of said second PAA layers;

forming a second photoresist pattern on top and bottom of said second Ni—

P seed layers;

plating second copper traces within said second photoresist patterns and through said at least one second via opening;

plating a surface finishing layer on said second copper traces; and

removing said second photoresist patterns and etching away said second Ni—

P seed layers not covered by said second copper traces to complete said flexible substrate.

19. The method according to claim 18 wherein said dielectric substrate comprises:

any kind of polyimide (PI), such as Kapton PI or Upisel PI, and liquid crystal polymer (LCP).

20. The method according to claim 18 wherein said alkaline modification comprises applying a KOH/alkaline base chemical to said dielectric substrate wherein said first and second PAA layers have a thickness of less than 100 nm and preferably less than 10 nm.

21. The method according to claim 18 further comprising depositing catalyst layers comprising Palladium (Pd) or Nickel (Ni) on said top and bottom PAA layers by immersion into an ionic metal solution to activate said first and second PAA layers for subsequent electroless Ni—

P seed layer plating.

22. The method according to claim 18 wherein said electrolessly plating said first and second Ni—

P seed layers is an autocatalytic process and wherein said first and second Ni—

P seed layers have a thickness of 0.1 μ

m+/−

10% and a composition of Ni;

96.5˜

97.5 wt % and P;

2.5˜

3.5 wt %.

23. The method according to claim 18 further comprising annealing said substrate after forming said first and second Ni—

P seed layers at 200°

C. for at least 10 minutes to at most 2 hours.

24. The method according to claim 18 wherein said plating said first and second copper traces comprises electrolytically plating copper to a thickness of between about 2 to 18 μ

m wherein a ratio of the top to bottom widths of said copper traces is close to 1, wherein an elongation strength of said copper traces is over 15%, wherein a tensile strength of said copper traces is between about 290 and 340 N/mm², wherein a hardness of said copper traces is 100 in vicker hardness with a purity of more than 99.9%, and wherein a center to center distance between two adjacent said copper traces is less than 8 μ

m.

25. The method according to claim 18 wherein said surface finishing layer comprises electrolytic Ni/Au, electroless Nickel/Immersion gold (ENIG), Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), electrolytic Palladium, electrolytic Titanium, electrolytic Tin, electrolytic Rhodium, Electroless Palladium/Autocatalytic Gold (EPAG), or Immersion Gold/Electroless Palladium/Immersion Gold (IGEPIG).