Semiconductor structure and manufacturing method thereof
First Claim
1. A method for manufacturing a semiconductor structure, the method comprising:
- forming a first dielectric layer over a gate structure and over a source drain structure adjacent to the gate structure, wherein a gate spacer extends along a sidewall of the gate structure, wherein a first portion of the gate spacer is disposed between the gate structure and the first dielectric layer, and a second portion of the gate spacer is disposed between the gate structure and the source drain structure;
forming a recess in the first dielectric layer over the source drain structure, wherein forming the recess removes a corner of the first portion of the gate spacer, wherein after forming the recess, the first portion of the gate spacer has a first sloped sidewall and a first straight sidewall;
forming a protection layer over the first dielectric layer and along the gate spacer, the protection layer lining sidewalls and a bottom of the recess;
deepening the recess to expose the source drain structure;
forming a bottom conductor in the recess and connected to the source drain structure;
forming a second dielectric layer over the gate structure and over the bottom conductor;
forming an opening in the second dielectric layer to expose the bottom conductor; and
forming an upper conductor in the opening and connected to the bottom conductor.
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Accused Products
Abstract
A semiconductor structure includes a substrate, a first gate structure, a first spacer, a source drain structure, a first dielectric layer, a conductor, and a protection layer. The first gate structure is present on the substrate. The first spacer is present on a sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The first dielectric layer is present on the first gate structure and has an opening therein, in which the source drain structure is exposed through the opening. The conductor is electrically connected to the source drain structure, in which the conductor has an upper portion in the opening of the first dielectric layer and a lower portion between the upper portion and the source drain structure. The protection layer is present between the lower portion and the first spacer and between the upper portion and the source drain structure.
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Citations
20 Claims
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1. A method for manufacturing a semiconductor structure, the method comprising:
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forming a first dielectric layer over a gate structure and over a source drain structure adjacent to the gate structure, wherein a gate spacer extends along a sidewall of the gate structure, wherein a first portion of the gate spacer is disposed between the gate structure and the first dielectric layer, and a second portion of the gate spacer is disposed between the gate structure and the source drain structure; forming a recess in the first dielectric layer over the source drain structure, wherein forming the recess removes a corner of the first portion of the gate spacer, wherein after forming the recess, the first portion of the gate spacer has a first sloped sidewall and a first straight sidewall; forming a protection layer over the first dielectric layer and along the gate spacer, the protection layer lining sidewalls and a bottom of the recess; deepening the recess to expose the source drain structure; forming a bottom conductor in the recess and connected to the source drain structure; forming a second dielectric layer over the gate structure and over the bottom conductor; forming an opening in the second dielectric layer to expose the bottom conductor; and forming an upper conductor in the opening and connected to the bottom conductor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for manufacturing a semiconductor structure, the method comprising:
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depositing a first dielectric material over a semiconductor device, the semiconductor device comprising; a gate structure; a mask layer over the gate structure; a spacer along a sidewall of the gate structure and along a sidewall of the mask layer; and a source drain structure adjacent to the gate structure, wherein the spacer is between the gate structure and the source drain structure, wherein the first dielectric material is deposited over the mask layer and the source drain structure; forming a recess in the first dielectric material directly over the source drain structure, wherein after the recess is formed, a first portion of the first dielectric material underlies the recess and covers the source drain structure, an upper portion of the spacer has a sloped sidewall, and a lower portion of the spacer has a straight sidewall; forming a protection layer lining sidewalls and a bottom of the recess; performing an anisotropic etch process to deepen the recess, wherein the source drain structure is exposed after the anisotropic etch process; and filling the recess with a first conductive material to form a bottom conductor. - View Dependent Claims (14, 15, 16)
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17. A method for manufacturing a semiconductor structure, the method comprising:
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forming a first dielectric layer over a gate structure and over a source drain structure adjacent to the gate structure, wherein a gate spacer extends along a sidewall of the gate structure and is between the gate structure and the source drain structure, wherein the first dielectric layer is formed along a portion of a sidewall of the gate spacer; forming a recess in the first dielectric layer over the source drain structure, a bottom of the recess being between the source drain structure and an upper surface of the first dielectric layer, wherein forming the recess removes a portion of the gate spacer such that an upper portion of the gate spacer has a sloped sidewall and a lower portion of the gate spacer has a straight sidewall; forming a protection layer along sidewalls and a bottom of the recess; deepening the recess by an anisotropic etch process to expose the source drain structure, wherein the anisotropic etch process removes the protection layer from the bottom of the recess, wherein after the anisotropic etch process, a remaining portion of the first dielectric layer extends along the sidewall of the gate structure; filling a first metal in the recess to form a bottom conductor that is electrically coupled to the source drain structure; forming a second dielectric layer over the gate structure and over the bottom conductor; forming an opening in the second dielectric layer to expose the bottom conductor; and filling a second metal in the opening to form an upper conductor that is electrically coupled to the bottom conductor. - View Dependent Claims (18, 19, 20)
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Specification