Structure and method of forming a joint assembly

• US 10,643,965 B2
• Filed: 09/01/2016
• Issued: 05/05/2020
• Est. Priority Date: 05/25/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ying-Ju, Su, An-Jhih, Chen, Hsien-Wei, Yeh, Der-Chyang, Wu, Chi-Hsi, Yu, Chen-Hua
• Primary Examiner(s): Tornow, Mark W
• Assistant Examiner(s): Rampersaud, Priya M
• Application Number:
  US15/254,758
• Publication Number:
  US 20170345786A1
• Time in Patent Office: 1,342 Days
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05017 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1144 by transfer printing
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11462 : Electroplating
• CPC Class Codes: H01L 2224/12105 : Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13019 : at the bonding interface of the bump connector, i.e. on the surface of the bump connector
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/27462 : Electroplating
• CPC Class Codes: H01L 2224/29026 : relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32148 : the layer connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81121 : Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• CPC Class Codes: H01L 2224/81125 : Bonding areas on the body
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/81895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/8191 : Cleaning, e.g. oxide removal step, desmearing
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1203 : Rectifying Diode
• CPC Class Codes: H01L 2924/1205 : Capacitor
• CPC Class Codes: H01L 2924/1206 : Inductor
• CPC Class Codes: H01L 2924/1207 : Resistor
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

providing a first semiconductor device and a second semiconductor device, the first semiconductor device comprising a first contact pad and a substrate, the first contact pad having a second surface contacting a metal feature of the substrate, the first contact pad having a first surface facing away from the substrate, the second semiconductor device comprising an encapsulant, a redistribution layer, and a second contact pad contacting the redistribution layer, the second contact pad having a third surface facing the first surface, the second contact pad having a fourth surface contacting the redistribution layer, the encapsulant contacting sidewalls of the redistribution layer, a top surface of the redistribution layer, and sidewalls of the second contact pad;

forming a substantially concave surface profile on one of the first surface or the third surface, the other of the first surface or the third surface having a substantially planar surface profile, wherein the second surface of the first contact pad or the fourth surface of the second contact pad comprising the other of the first surface or the third surface has a first width, wherein the other of the first surface or the third surface has a second width, and wherein a ratio of the second width to the first width is 5;

2;

electroplating a solder layer on the first surface of the first contact pad, the solder layer having a fifth surface facing away from the first surface, wherein the first surface and the fifth surface have a same surface contour profile;

aligning the solder layer over the second contact pad;

landing the fifth surface of the solder layer directly on the third surface of the second contact pad; and

bonding the solder layer to the second contact pad to form a joint structure, the joint structure having a sixth surface in contact with the first surface, the sixth surface having a third width equal to a width of the first surface, the joint structure having a seventh surface in contact with the third surface, the seventh surface having a fourth width equal to a width of the third surface, the joint structure having sidewalls which taper from the third width to the fourth width.

2. The method of claim 1, wherein providing the first semiconductor device comprises providing an integrated passive device (IPD).

3. The method of claim 2, wherein providing the IPD further comprises providing an impedance matching circuit, a harmonic filter, a bandpass filter, a low pass filter, a high pass filter, a coupler, a balun, a power combiner, or a power divider.

4. The method of claim 2, wherein providing the IPD further comprises providing a capacitor, a resistor, an inductor, or a diode.

5. The method of claim 1, wherein providing the second semiconductor device comprises providing a Package-on-Package (PoP) device.

6. The method of claim 1, wherein the substantially planar surface profile is formed on the second contact pad or the first contact pad prior to bonding the solder layer to the second contact pad.

7. The method of claim 1, wherein the substantially concave surface profile is formed with a cavity depth from about 1 μ

m to about 7 μ

m.

8. A method of forming a semiconductor device, the method comprising:

providing a first semiconductor device and a second semiconductor device, the second semiconductor device comprising a contact pad, the contact pad having a first substantially planar surface and a second surface opposite the first substantially planar surface, the second surface contacting a metal feature, the second surface having a first width, the first substantially planar surface having a second width, wherein a ratio of the second width to the first width is 5;

2, wherein the first substantially planar surface is an outermost surface of the contact pad;

electroplating a solder layer on a second contact pad of the first semiconductor device, the solder layer having a second substantially planar surface, the second contact pad having a first surface facing the solder layer, the first surface having a third width and being substantially planar, the second contact pad having a third surface opposite the first surface, the third surface having a fourth width, wherein a ratio of the third width to the second width is 5;

2;

aligning the first substantially planar surface over the second substantially planar surface;

landing the first substantially planar surface on the second substantially planar surface, wherein the first substantially planar surface directly adjoins the second substantially planar surface; and

bonding the first substantially planar surface to the second substantially planar surface with a joint structure being formed from the solder layer between the second contact pad and the contact pad, wherein the joint structure has tapered sidewalls continuously diminishing from a fifth width at a fourth surface of the joint structure adjoining the second contact pad to a sixth width at a fifth surface of the joint structure adjoining the contact pad, the fifth width being equal to the third width, and the sixth width being equal to the second width.

9. The method of claim 8, wherein providing the first semiconductor device comprises providing an integrated passive device (IPD).

10. The method of claim 9, wherein providing the IPD further comprises providing an impedance matching circuit, a harmonic filter, a bandpass filter, a low pass filter, a high pass filter, a coupler, a balun, a power combiner, or a power divider.

11. The method of claim 9, wherein providing the IPD comprises providing a capacitor, a resistor, an inductor, or a diode.

12. The method of claim 9, wherein providing the second semiconductor device comprises providing a Package-on-Package (PoP) device.

13. A method, comprising:

forming a first semiconductor device, wherein forming the first semiconductor device comprises disposing a first contact pad over an integrated passive device (IPD), wherein a first portion of the first contact pad is disposed in a first recess of the first semiconductor device, the first portion is coupled to the IPD, and the first contact pad has a first surface opposite the IPD, the first surface comprising first lateral extents spanning a first distance;

forming a second semiconductor device, wherein forming the second semiconductor device comprises disposing a second contact pad over a redistribution layer (RDL), wherein a second portion of the second contact pad is disposed in a second recess of the second semiconductor device, the second portion is coupled to the RDL, the second portion has tapered sidewalls, a third portion of the second contact pad extends over a topmost surface of the second semiconductor device, the third portion has vertical sidewalls, and the second contact pad has a second surface opposite the RDL, the second surface comprising second lateral extents spanning a second distance, wherein the second distance is less than the first distance;

electroplating a solder layer on the first surface of the first contact pad; and

after the electroplating, forming a joint structure between the first semiconductor device and the second semiconductor device, wherein forming the joint structure comprises reflowing the solder layer between the first contact pad and the second contact pad, wherein after the reflowing, the solder layer has a tapered sidewall profile extending with a continuously diminishing width from the first surface to the second surface, the solder layer comprising a third surface proximal the first contact pad and a fourth surface proximal the second contact pad, the third surface having third lateral extents spanning a third distance equal to the first distance, the fourth surface having fourth lateral extents spanning a fourth distance equal to the second distance, wherein at least one of the first surface or the second surface is substantially planar, wherein the first contact pad comprises a fifth surface coupled to the IPD, the fifth surface having fifth lateral extents spanning a fifth distance, wherein the second contact pad comprises a sixth surface coupled to the RDL, the sixth surface having sixth lateral extents spanning a sixth distance, wherein at least one of a ratio of the first distance to the fifth distance or a ratio of the second distance to the sixth distance is 5;

2.

14. The method of claim 13, wherein:

forming the first semiconductor device further comprises the first distance being less than or equal to about 50 μ

m;

forming the second semiconductor device further comprises the second distance being less than or equal to about 49 μ

m;

forming the first semiconductor device further comprises a first width of the first recess being less than or equal to about 20 μ

m; and

forming the second semiconductor device further comprises a second width of the second recess being less than or equal to about 20 μ

m.

15. The method of claim 13, wherein at least one of:

forming the first semiconductor device further comprises the first contact pad comprising copper;

forming the second semiconductor device further comprises the second contact pad comprising copper;

or

forming the joint structure further comprises the solder layer comprising tin.

16. The method of claim 13, wherein forming the second semiconductor device further comprises the second semiconductor device comprising a Package-on-Package (PoP) device.

17. The method of claim 16, wherein forming the first semiconductor device further comprises the IPD comprising a capacitor, a resistor, an inductor, or a diode.

18. The method of claim 17, wherein forming the first semiconductor device further comprises the first semiconductor device comprising an impedance matching circuit, a harmonic filter, a bandpass filter, a low pass filter, a high pass filter, a coupler, a balun, a power combiner, or a power divider.

19. The method of claim 13, wherein forming the joint structure further comprises the solder layer comprising a substantially continuous distribution of material.

20. The method of claim 19, wherein forming the joint structure further comprises the solder layer having third lateral extents spanning a third distance, wherein the third distance is less than or equal to the second distance.