Apparatuses and memory devices including control logic levels, and related electronic systems

• US 10,643,991 B2
• Filed: 06/17/2019
• Issued: 05/05/2020
• Est. Priority Date: 12/29/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sills, Scott E., Beigel, Kurt D.
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US16/443,628
• Publication Number:
  US 20190304970A1
• Time in Patent Office: 323 Days
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H03K 19/0948 : using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/20 : characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H10B 61/22 : of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/00 : Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting transistors laterally displaced from one another. A memory device, a thin film transistor control logic assembly, an electronic system, and a method of operating a semiconductor device are also described.

Claims

1. An apparatus, comprising:

a first deck overlying and in electrical communication with base control logic structure, the first deck comprising;

a first memory element level comprising first memory elements; and

a first control logic level in electrical communication with the first memory element level and comprising first CMOS devices individually exhibiting first horizontally-neighboring transistors; and

a second deck overlying the first deck and in electrical communication with base control logic structure, the second deck comprising;

a second memory element level comprising second memory elements; and

a second control logic level in electrical communication with the second memory element level and comprising second CMOS devices individually exhibiting second horizontally-neighboring transistors.

2. The apparatus of claim 1, further comprising:

a first access device level in electrical communication with and vertically intervening between the first memory element level and the first control logic level, the first access device level comprising first access devices electrically coupled to the first memory elements of the first memory element level; and

a second access device level in electrical communication with and vertically intervening between the second memory element level and the second control logic level, the second access device level comprising second access devices electrically coupled to the second memory elements of the second memory element level.

3. The apparatus of claim 1, wherein:

the first memory element level further comprises first access devices electrically coupled to the first memory elements; and

the second memory element level further comprises second access devices electrically coupled to the second memory elements.

4. The apparatus of claim 1, wherein:

the first horizontally-neighboring transistors of one or more of the first CMOS devices comprise;

a first vertical PMOS transistor; and

a first vertical NMOS transistor horizontally neighboring the first vertical PMOS transistor; and

the second horizontally-neighboring transistors of one or more of the second CMOS devices comprise;

a second vertical PMOS transistor; and

a second vertical NMOS transistor horizontally neighboring the second vertical PMOS transistor.

5. The apparatus of claim 4, wherein the first vertical PMOS transistor, the first vertical NMOS transistor, the second vertical PMOS transistor, and the second vertical NMOS transistor each individually exhibit a double-gate configuration.

6. The apparatus of claim 4, wherein the first vertical PMOS transistor, the first vertical NMOS transistor, the second vertical PMOS transistor, and the second vertical NMOS transistor each individually exhibit a single-gate configuration.

7. The apparatus of claim 4, wherein the first vertical PMOS transistor, the first vertical NMOS transistor, the second vertical PMOS transistor, and the second vertical NMOS transistor each individually exhibit a gate-all-around configuration.

8. The apparatus of claim 1, wherein:

the first horizontally-neighboring transistors of one or more of the first CMOS devices comprise;

a first horizontal PMOS transistor; and

a first horizontal NMOS transistor horizontally neighboring the first horizontal PMOS transistor; and

the second horizontally-neighboring transistors of one or more of the second CMOS devices comprise;

a second horizontal PMOS transistor; and

a second horizontal NMOS transistor horizontally neighboring the second horizontal PMOS transistor.

9. The apparatus of claim 8, wherein the first horizontal PMOS transistor, the first horizontal NMOS transistor, the second horizontal PMOS transistor, and the second horizontal NMOS transistor each individually exhibit a top-gate configuration.

10. The apparatus of claim 8, wherein the first horizontal PMOS transistor, the first horizontal NMOS transistor, the second horizontal PMOS transistor, and the second horizontal NMOS transistor each individually exhibit a bottom-gate configuration.

11. The apparatus of claim 1, wherein:

the first horizontally-neighboring transistors of one or more of the first CMOS devices comprise;

a first PMOS FinFET; and

a first NMOS FinFET horizontally neighboring the first PMOS FinFET; and

the second horizontally-neighboring transistors of one or more of the second CMOS devices comprise;

a second PMOS FinFET; and

a second NMOS FinFET horizontally neighboring the second PMOS FinFET.

12. A memory device, comprising:

multiple tiers each individually comprising;

a memory level comprising memory elements; and

a control logic level in electrical communication with the memory element level and comprising CMOS devices each individually comprising;

an NMOS transistor; and

a PMOS transistor horizontally displaced from the NMOS transistor.

13. The memory device of claim 12, further comprising a base control logic structure in electrical communication with the control logic level of each of the multiple tiers, the base control logic structure comprising one or more of charge pumps, delay-locked loop devices, and drain supply voltage regulators.

14. The memory device of claim 13, the control logic level of each of the multiple tiers comprises devices each individually including one or more of the CMOS devices, the devices selected from the group comprising decoders, sense amplifiers, word line drivers, repair devices, memory test devices, multiplexers, error checking and correction devices, and self-refresh/wear leveling devices.

15. The memory device of claim 12, wherein:

the memory level of each of the multiple tiers has substantially the same configuration as the memory level of each other of the multiple tiers; and

the control logic level of each of the multiple tiers has substantially the same configuration as the control logic level of each other of the multiple tiers.

16. The memory device of claim 12, wherein:

the NMOS transistor comprises a vertical NMOS transistor; and

the PMOS transistor comprises a vertical PMOS transistor.

17. The memory device of claim 12, wherein:

the NMOS transistor comprises a horizontal NMOS transistor; and

the PMOS transistor comprises a horizontal PMOS transistor.

18. The memory device of claim 12, wherein:

the NMOS transistor comprises an NMOS FinFET; and

the PMOS transistor comprises a PMOS FinFET.

19. The memory device of claim 12, wherein each of the multiple tiers further comprises an access device level between and in electrically communication with the memory level and the control logic level, the access device level comprising access devices electrically coupled to the memory elements of the memory level.

20. An electronic system, comprising:

at least one apparatus comprising;

multiple decks each individually comprising;

a memory element level comprising memory elements;

an access device level comprising access devices electrically coupled to the memory elements of the memory element level; and

a control logic level in electrical communication with the memory element level and the access device level, the control logic level comprising at least one thin film transistor CMOS device comprising;

an NMOS transistor; and

a PMOS transistor horizontally neighboring the NMOS transistor.