Semiconductor device

• US 10,643,992 B2
• Filed: 01/29/2019
• Issued: 05/05/2020
• Est. Priority Date: 02/19/2018
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Naito, Tatsuya
• Primary Examiner(s): Ho, Tu-Tu V
• Application Number:
  US16/260,117
• Publication Number:
  US 20190259748A1
• Time in Patent Office: 462 Days
• Field of Search: 257368
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0716 in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0804 Emitter regions of bipolar transistors
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/083 Anode or cathode regions of thyristors or gated bipolar-mode devices
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes

Abstract

A semiconductor device is provided, the semiconductor device including: a semiconductor substrate having a first-conductivity-type drift region; one or more transistor portions provided in the semiconductor substrate; and one or more diode portions provided in the semiconductor substrate, wherein both the transistor portions and the diode portions have trench portions that lie from a top surface of the semiconductor substrate to the drift region and include conductive portions, and in a top view of the semiconductor substrate, a main direction of the trench portions in the transistor portions is different from a main direction of the trench portions in the diode portions.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first-conductivity-type drift region;

one or more transistor portions provided in the semiconductor substrate; and

one or more diode portions provided in the semiconductor substrate, wherein

both the transistor portions and the diode portions have trench portions that lie from a top surface of the semiconductor substrate to the drift region and include conductive portions, and

in a top view of the semiconductor substrate, a main direction of the trench portions in the transistor portions is different from a main direction of the trench portions in the diode portions.

2. The semiconductor device according to claim 1, wherein in the top view of the semiconductor substrate, the main direction of the trench portions in the transistor portions is orthogonal to the main direction of the trench portion in the diode portions.

3. The semiconductor device according to claim 1, further comprising:

a second-conductivity-type first well region that;

is provided in the semiconductor substrate to overlap, in the top view of the semiconductor substrate, end portions of a plurality of the trench portions in the transistor portions; and

has a longitudinal direction in a first direction which is different from the main direction of the trench portions in the transistor portions; and

a second-conductivity-type second well region that;

is provided in the semiconductor substrate to overlap, in the top view of the semiconductor substrate, end portions of a plurality of the trench portions in the diode portions; and

has a longitudinal direction in a second direction different from the main direction of the trench portions in the diode portions.

4. The semiconductor device according to claim 3, wherein the first well region is continuous with the second well region.

5. The semiconductor device according to claim 4, wherein in the top view of the semiconductor substrate:

the first well region extends to a position at which the first well region faces the diode portions; and

the diode portions are surrounded by the first well region and the second well region.

6. The semiconductor device according to claim 3, further comprising a lifetime control region that is provided on a top surface side of the semiconductor substrate and contains a lifetime killer, wherein

the transistor portions have gate trench portions that lie from the top surface of the semiconductor substrate to the drift region, and include conductive portions, and

the lifetime control region is provided in the diode portions, and is not provided below the gate trench portions in the transistor portions.

7. The semiconductor device according to claim 6, further comprising:

a contact hole that is provided;

above the semiconductor substrate; and

to overlap the transistor portions; and

a contact hole that is provided;

above the semiconductor substrate; and

to overlap the diode portions, wherein

in the top view of the semiconductor substrate, a main direction of the contact hole provided to overlap the transistor portions is orthogonal to a main direction of the contact hole provided to overlap the diode portions.

8. The semiconductor device according to claim 6, further comprising a contact hole provided above the first well region extending, in the top view of the semiconductor substrate, to a position at which the first well region faces the diode portions.

9. The semiconductor device according to claim 8, wherein in the top view of the semiconductor substrate, the lifetime control region overlaps the contact hole provided above the first well region.