Semiconductor device with metal gates

• US 10,643,997 B2
• Filed: 07/17/2017
• Issued: 05/05/2020
• Est. Priority Date: 05/19/2016
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Feng, Li-Wei, Huang, Tong-Jyun, Tsai, Shih-Hung, Wu, Jia-Rong, Chan, Tien-Chen, Lin, Yu-Shu, Jenq, Jyh-Shyang
• Primary Examiner(s): Sandvik, Benjamin P
• Application Number:
  US15/652,223
• Publication Number:
  US 20170338227A1
• Time in Patent Office: 1,023 Days
• Field of Search: None
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor device includes at least a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.

Claims

1. A semiconductor device, comprising:

a substrate, having a first region and a second region;

a plurality of fin-shaped structures, respectively disposed in the first region and the second region;

a protection layer, conformally covering the surface of the substrate and the sidewalls of the fin-shaped structures in the first region and the second region;

a plurality of epitaxial layers, respectively and conformally disposed on and in direct contact with the fin-shaped structures in the first region, wherein vertical surfaces of the epitaxial layers in the first region is flush with outer vertical surfaces of the fin-shaped structures in the first region;

a plurality of another epitaxial layers, respectively and conformally disposed on the epitaxial layers in the first region and on the fin-shaped structures in the second region, wherein a surface of the another epitaxial layer in the first region is flush with a vertical surface of the protection layer in the first region; and

a gate electrode, covering the fin-shaped structures in the second region, wherein the protection layer in the second region is disposed below the gate electrode.

2. The semiconductor device of claim 1, wherein each of the fin-shaped structures in the first region comprises stair-shaped sidewalls.

3. The semiconductor device of claim 1, the semiconductor device further comprising a shallow trench isolation structure disposed on the substrate, wherein each of the fin-shaped structures in the first region comprises a tread being level with a top surface of the shallow trench isolation structure.

4. The semiconductor device of claim 3, wherein each of the epitaxial layers is in direct contact with each of the treads.

5. The semiconductor device of claim 1, wherein the semiconductor device further comprising another gate electrode covering each of the epitaxial layers in the first region.