Semiconductor memory device having an electrically floating body transistor

• US 10,644,001 B2
• Filed: 10/30/2018
• Issued: 05/05/2020
• Est. Priority Date: 10/04/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US16/174,377
• Publication Number:
  US 20190067289A1
• Time in Patent Office: 553 Days
• Field of Search: 365189011, 257368
• CPC Class Codes: G11C 11/04 using storage elements having cylindrical form, e.g. rod, wire G11C11/12, G11C11/14 take precedence
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 11/4026 using bipolar transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.

Claims

1. An array of memory cells formed in a semiconductor, the array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and a plurality of columns wherein the rows of memory cells define a first direction and the columns of memory cells define a second direction, and each of said memory cells comprising;

a bipolar device having a floating base region, a first region, a second region, and a gate region wherein;

a state of said semiconductor memory cell is stored in said floating base region;

said first region is located at a surface of said floating base region;

said second region is located below said floating base region, said second region is commonly connected to at least two of said semiconductor memory cells in said matrix; and

said gate region overlays two of said semiconductor memory cells along the column direction,

wherein said bipolar device is activated by electrical signals provided to said second region when the memory cell is in one of said first and second states, and

wherein said bipolar device is not activated by electrical signals provided to said second region when the memory cell is in the other of said first and second states.

2. The array of semiconductor memory cells of claim 1, further comprising a plurality of source lines crossing the array in a first direction beneath said surface, wherein the plurality of source lines are coupled to said second regions.

3. The array of semiconductor memory cells of claim 1, further comprising a plurality of bit lines crossing the array in a second direction substantially orthogonal to the first direction, wherein the plurality of bit lines are coupled at said surface to said first regions.

4. The array of semiconductor memory cells of claim 1, further comprising a plurality of word lines crossing the array in a first direction above said surface, wherein the plurality of word lines are coupled to said gate regions.

5. The array of semiconductor memory cells of claim 1, further comprising a first well region of a first conductivity type beneath a buried region.

6. The array of semiconductor memory cells of claim 1, wherein each of said second regions is adapted to receive electrical signals of different amplitude or polarity, wherein the electrical signals depend on an operation of each of said memory cells.

7. The array of semiconductor memory cells of claim 6, wherein said electrical signal applied to said second region comprises a pulse.

8. The array of semiconductor memory cells of claim 6, wherein said electrical signal applied to said second region comprises a constant amplitude level.

9. The array of semiconductor memory cells of claim 1, wherein said array is formed in a fin structure fabricated on said semiconductor.

10. An integrated circuit comprising:

an array of memory cells formed in a semiconductor, the array comprising;

a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell of the plurality of memory cells comprising;

a bipolar device having a floating base region, a first region, a second region, and a gate region wherein;

a state of said semiconductor memory cell is stored in said floating base region, said floating base region having a surface;

said first region is located at the surface of said floating base region;

said second region is located below said floating base region, said second region is commonly connected to at least two of said semiconductor memory cells in said matrix; and

said gate region overlays two of said semiconductor memory cells along the column direction, and a first control circuitry configured to provide electrical signals to said second region,

wherein said bipolar device is activated by said electrical signals provided to said second region when the memory cell is in one of said first and second states, and

wherein said bipolar device is not activated by said electrical signals provided to said second region when the memory cell is in the other of said first and second states.

11. The integrated circuit of claim 10, further comprising a plurality of source lines crossing the array in a first direction beneath one or more surfaces of said plurality of semiconductor memory cells, wherein the plurality of source lines are coupled to one or more second regions of said plurality of semiconductor memory cells.

12. The integrated circuit of claim 11, further comprising a plurality of bit lines crossing the array in a second direction substantially orthogonal to the first direction, wherein the plurality of bit lines are coupled to one or more said first regions.

13. The integrated circuit of claim 10, further comprising a plurality of word lines crossing the array in a first direction above one or more surfaces, wherein the plurality of word lines are coupled to one or more gate regions.

14. The integrated circuit of claim 10, further comprising second control circuitry configured to provide electrical signals to said first region.

15. The integrated circuit of claim 10, wherein said electrical signals to said second region have an amplitude or polarity dependent on an operation of said array of memory cells.

16. The integrated circuit of claim 10, wherein said first control circuitry comprises a voltage generator circuit.

17. The integrated circuit of claim 16, further comprising a multiplexer electrically connected between said voltage generator circuit and said second region, said multiplexer configured to apply periodic pulses of positive voltage to said second region.

18. The integrated circuit of claim 10, wherein said first control circuitry comprises a reference generator circuit configured to sense potential of said floating base region.

19. The integrated circuit of claim 14, wherein said second control circuitry comprises a read circuit connected to said first region and configured to read a state of said semiconductor memory cell.

20. The integrated circuit of claim 19, further comprising a reference generator circuit connected to said read circuit.