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Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle

  • US 10,644,002 B2
  • Filed: 01/08/2019
  • Issued: 05/05/2020
  • Est. Priority Date: 08/05/2008
  • Status: Active Grant
First Claim
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1. A semiconductor memory cell comprising:

  • a first silicon controlled rectifier device having a first region, a first floating body region, a first buried layer region, and a first substrate region;

    a second silicon controlled rectifier device having a second region, a second floating body region, a second buried layer region, and a second substrate region;

    a transistor comprising said first region, said first floating body region, said second region, and a gate;

    wherein said first floating body region is common to said second floating body region;

    wherein said first buried layer region is common to said second buried layer region;

    wherein said first substrate region is common to said second substrate region;

    wherein said transistor is usable to access said memory cell; and

    wherein a state of said memory cell is maintained through a positive voltage applied to said first and second substrate regions.

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