Semiconductor memory devices having bit line node contact between bit line and active region

• US 10,644,003 B2
• Filed: 07/27/2017
• Issued: 05/05/2020
• Est. Priority Date: 12/02/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Min Hee, Yamada, Satoru, Kim, Junsoo, Park, Honglae, Lee, Wonsok, Jeon, Namho
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US15/661,121
• Publication Number:
  US 20180158826A1
• Time in Patent Office: 1,013 Days
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A semiconductor memory device includes a substrate having an active region, word lines extending across the active region, a bit line on the active region between the word lines, a bit line node contact between the bit line and the active region, and a storage node contact on an end portion of the active region, wherein one or more of the bit line node contact or the storage node contact include silicon germanium.

Claims

1. A semiconductor memory device, comprising:

a substrate including an active region;

word lines extending across the active region in a first direction;

a bit line on the active region between the word lines, the bit line extending in a second direction crossing the first direction;

a bit line node contact between the bit line and the active region;

a storage node contact extending from an end portion of the active region beyond a top surface of the substrate, the storage node contact including a lower portion below the top surface of the substrate and an upper portion above the top surface of the substrate, wherein the lower and upper portions of the storage node contact include silicon germanium;

a first semiconductor pattern surrounding sidewalls and a bottom surface of each of the word lines, wherein the first semiconductor pattern includes a silicon germanium layer or a Group III-V compound semiconductor layer; and

a second semiconductor pattern between the first semiconductor pattern and each of the word lines, wherein the second semiconductor pattern includes a semiconductor material different from that of the first semiconductor pattern.

2. The semiconductor memory device as claimed in claim 1, further comprising:

source/drain regions in a portion of the active region below the bit line node contact and in a portion of the active region below the storage node contact, wherein the source/drain regions include a trivalent impurity element.

3. The semiconductor memory device as claimed in claim 2, wherein the trivalent impurity element includes boron (B) or indium (In).

4. The semiconductor memory device as claimed in claim 1, wherein the first semiconductor pattern includes a silicon layer and wherein the substrate is one of a silicon germanium substrate or a Group III-V compound semiconductor substrate.

5. The semiconductor memory device as claimed in claim 1, wherein one or more of the bit line node contact or the storage node contact are doped with boron.

6. The semiconductor memory device as claimed in claim 1, wherein the bit line node contact extends from the active region beyond the top surface of the substrate, and includes a lower portion below the top surface of the substrate and an upper portion above the top surface of the substrate, and wherein the lower and upper portions of the bit line node contact include silicon germanium.