Dense arrays and charge storage devices

• US 10,644,021 B2
• Filed: 05/04/2018
• Issued: 05/05/2020
• Est. Priority Date: 08/14/2000
• Status: Expired due to Term

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Lee, Thomas H., Kouznetsov, Igor G.
• Primary Examiner(s): Ha, Nathan W
• Application Number:
  US15/971,293
• Publication Number:
  US 20180254286A1
• Time in Patent Office: 732 Days
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5612 Multilevel memory cell with more than one floating gate
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42364 : characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/511 : with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7391 : Gated diode structures
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7889 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/861 : Diodes
• CPC Class Codes: H01L 29/8616 : Charge trapping diodes
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/60 : Peripheral circuit regions
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/23 : with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Claims

1. An array of nonvolatile memory cells, comprising a monolithic three dimensional memory array that comprises N device levels that are vertically stacked and separated from each other, wherein N is an integer greater than 1;

wherein each device level of the N device levels includes a respective two-dimensional array of memory cells, and N two-dimensional arrays of memory cells are vertically stacked within the array; and

wherein each memory cell comprises a semiconductor device and each memory cell size per bit is about (2f²)/N, where f is a minimum feature size.

2. The array of claim 1, wherein

the semiconductor device comprises a TFT EEPROM comprising a channel, source and drain regions, and a charge storage region.

3. The array of claim 2, further comprising:

a plurality of bit lines arranged in columns in each of the N device levels, each bit line contacting the source or the drain regions of the TFT EEPROMs, wherein the bit lines extend substantially perpendicular to a source-channel-drain direction of the TFT EEPROMs within a respective device level;

a plurality of word lines arranged in rows in each of the N device levels, and the words lines extend substantially parallel to the source-channel-drain direction of the TFT EEPROMs within a respective device level; and

at least one interlayer insulating layer located between the device levels.

4. The array of claim 3, wherein:

the TFT EEPROMs further comprise control gates; and

the plurality of word lines are self aligned to the control gates of the respective TFT EEPROMs, to the channel regions of the respective TFT EEPROMs, and to the charge storage regions of the respective TFT EEPROMs located below the respective word lines.

5. The array of claim 4, wherein the TFT EEPROMs further comprise:

sidewall spacers located adjacent to sidewalls of the gates of the TFT EEPROMs, wherein the sidewall spacers have approximately the same height as the gates; and

an intergate insulating layer which is located between the sidewall spacers, and above the source and the drain regions of the TFT EEPROMs in each device layer, and wherein the intergate insulating layer has approximately the same height as the sidewall spacers.

6. The array of claim 5, wherein:

the word lines are located on the sidewall spacers and on the intergate insulating layer in each device level; and

the word lines contact the respective TFT EEPROM control gates through an opening between the sidewall spacers.

7. The array of claim 3, wherein the TFT EEPROMs further comprise:

floating gates located in the charge storage regions;

sidewall spacers located adjacent to sidewalls of the floating gates of the TFT EEPROMs;

an intergate insulating layer which is located between the sidewall spacers, and above the source and the drain regions of the TFT EEPROMs in each device layer, and wherein the intergate insulating layer has approximately the same height as the sidewall spacers; and

a control gate dielectric located above the sidewall spacers and the intergate insulating layer and below the word lines.

8. The array of claim 7, wherein the floating gates extend vertically and laterally above the sidewall spacers, such that the floating gates have a “

T”

shape.

9. The array of claim 3, further comprising word line contacts and bit line contacts which connect the word lines and the bit lines with peripheral circuits located in a semiconductor substrate below the first device level of the array;

and

wherein the bit line contacts extend between plural device layers.

10. The array of claim 1, wherein each device level includes a two-dimensional array of charge storage regions, a plurality of bit lines extending below bottom surfaces of the two-dimensional array of charge storage regions, and a plurality of word lines located above top surfaces of the two-dimensional array of charge storage regions.

11. The array of claim 10, wherein:

each device level includes a two-dimensional array of channel regions; and

each channel region contacts a bottom surface of a respective charge storage region of the two-dimensional array of charge storage regions.

12. The array of claim 11, wherein each charge storage region of the two-dimensional array of charge storage regions contacts a pair of bit lines within the plurality of bit lines.

13. The array of claim 12, wherein each bit line comprises a vertical stack including, from top to bottom, a silicide region and a transistor source and drain region.

14. The array of claim 13, wherein:

the silicide region contacts a sidewall of a respective charge storage region within the two-dimensional array of charge storage regions; and

the transistor source and drain region contacts a bottom surface of the respective charge storage region within the two-dimensional array of charge storage regions.

15. The array of claim 10, wherein the plurality of bit lines overlies, and is vertically spaced from, the plurality of word lines.

16. The array of claim 15, wherein each device level includes a two-dimensional array of gate electrodes that overlies the two-dimensional array of charge storage regions.

17. The array of claim 16, wherein:

each device level includes a two-dimensional array of pairs of gate stack sidewall spacers that contact sidewalls of a respective gate electrode within the two-dimensional array of gate electrodes; and

the plurality of bit lines contacts top surfaces of the two-dimensional array of pairs of gate stack sidewall spacers.

18. The array of claim 17, wherein each gate stack sidewall spacer includes a sidewall that contacts an insulating material portion which contacts a top surface of a respective bit line and a bottom surface of a respective word line.

19. The array of claim 16, wherein each gate electrode within the two-dimensional array of gate electrodes contacts, or is electrically shorted to, a respective one of the plurality of word lines.

20. The array of claim 16, wherein each device level includes a two-dimensional array of control gate dielectrics that contacts a respective gate electrode within the two-dimensional array of gate dielectrics and underlies the plurality of word lines.