Method of processing a substrate and a device manufactured by using the method

• US 10,644,025 B2
• Filed: 09/28/2018
• Issued: 05/05/2020
• Est. Priority Date: 11/07/2016
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holding B.V. (ASM International NV)
• Inventors: Chun, Seung Ju, Yoo, Yong Min, Choi, Jong Wan, Kim, Young Jae, Kim, Sun Ja, Lim, Wan Gyu, Min, Yoon Ki, Lee, Hae Jin, Yoo, Tae Hee
• Primary Examiner(s): Smith, Zandra V
• Assistant Examiner(s): Joy, Jeremy J
• Application Number:
  US16/147,047
• Publication Number:
  US 20190035810A1
• Time in Patent Office: 585 Days
• CPC Class Codes: C23C 16/345 Silicon nitride
• CPC Class Codes: C23C 16/4554 Plasma being used non-continuously in between ALD reactions C23C16/56 takes precedence
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

Claims

1. A semiconductor device comprising:

a substrate;

at least one memory cell string extending to protrude from the substrate;

a first word line connected to a first memory cell of the memory cell string; and

a second word line connected to a second memory cell of the memory cell string, wherein at least one of the first and second word lines comprises;

a first conductive layer extending toward a channel;

a second conductive layer on the first conductive layer; and

a third conductive layer on the second conductive layer,

wherein the second conductive layer and the third conductive layer have different sidewall profiles, and

wherein, with respect to one side surface of the second conductive layer and the third conductive layer, one end of the third conductive layer protrudes from a side surface of the second conductive layer.

2. The semiconductor device of claim 1, wherein

the first conductive layer comprises a groove, and

the groove is formed adjacent to the second conductive layer.

3. The semiconductor device of claim 1, wherein, with respect to another side surface of the second conductive layer and the third conductive layer, one end of the second conductive layer protrudes from a side surface of the third conductive layer.

4. The semiconductor device of claim 1, wherein the at least one word line has an overhang structure.

5. The semiconductor device of claim 4, wherein the overhang structure is a parallelogram-like overhang structure.

6. The semiconductor device of claim 1, further comprising:

a first insulation layer on the substrate; and

a second insulation layer on the first insulation layer.

7. The semiconductor device of claim 6, wherein the first insulation layer and the second insulation layer have different sidewall profiles.

8. The semiconductor device of claim 6, wherein the first insulation layer and the second insulation layer have different densities and different WERs.

9. The semiconductor device of claim 8, wherein the first insulation layer is less dense than the second insulation layer.

10. The semiconductor device of claim 6, wherein the first insulation layer and the second insulation layer include a silicon nitride.

11. The semiconductor device of claim 10, wherein the first insulation layer has a smaller number of Si—

N bonds than the second insulation layer.

12. The semiconductor device of claim 6, wherein, with respect to one side surface of the first insulation layer and the second insulation layer, one end of the second insulation layer protrudes from a side surface of the first insulation layer.

13. The semiconductor device of claim 12, wherein, with respect to another side surface of the first insulation layer and the second insulation layer, one end of the first insulation layer protrudes from a side surface of the second insulation layer.

14. A semiconductor device comprising:

a substrate;

a channel protruding from the substrate; and

at least one word line extending toward the channel,

wherein the at least one word line has an overhang structure,

wherein the conductive word line structure comprises;

a first conductive layer extending toward a channel;

a second conductive layer on the first conductive layer; and

a third conductive layer on the second conductive layer,

wherein, with respect to one side surface of the second conductive layer and the third conductive layer, one end of the third conductive layer protrudes from a side surface of the second conductive layer.

15. The semiconductor device of claim 14, wherein the overhang structure is a parallelogram-like overhang structure.

16. The semiconductor device of claim 14, wherein

the second conductive layer and the third conductive layer have different sidewall profiles.