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Vertical memory device

  • US 10,644,028 B2
  • Filed: 03/19/2019
  • Issued: 05/05/2020
  • Est. Priority Date: 07/21/2017
  • Status: Active Grant
First Claim
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1. A vertical memory device comprising:

  • a substrate having a cell array region and a connection region adjacent to the cell array region;

    a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and the plurality of gate electrode layers form a stepped structure in the connection region; and

    at least one first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, wherein a depth of a lower end portion of the at least one first metal line at an edge portion of the connection region is greater than a depth of a lower end portion of the at least one first metal line in the cell array region, based on an upper surface of the substrate, and wherein a height from the upper surface of the substrate to an upper surface of an uppermost gate electrode layer among the plurality of gate electrode layers is about 4.4 μ

    m or more.

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