Array substrate, manufacturing method thereof, and display panel

• US 10,644,040 B2
• Filed: 07/25/2018
• Issued: 05/05/2020
• Est. Priority Date: 02/26/2018
• Status: Active Grant

• Current Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Chen, Chen
• Primary Examiner(s): Gheyas, Syed I
• Application Number:
  US16/044,948
• Publication Number:
  US 20190267408A1
• Time in Patent Office: 650 Days
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

The present invention discloses an array substrate for forming a display panel, comprising: a substrate; a thin-film transistor disposed on the substrate, the thin-film transistor comprising a drain electrode; a planarization layer disposed on the thin-film transistor, the planarization layer being provided with a first via hole for exposing the drain electrode; a pixel electrode layer disposed on the surface of the planarization layer away from the substrate, the pixel electrode layer covering the first via hole and being in contact with the drain electrode; and a photoresist layer covering the pixel electrode layer, and the photoresist layer filling the first via hole which is covered with the pixel electrode layer. The present invention solves the issues caused by the height difference in products.

Claims

1. An array substrate for forming a display panel, comprising:

a substrate;

a thin-film transistor disposed on the substrate, the thin-film transistor comprising a drain electrode;

a planarization layer disposed on the thin-film transistor, the planarization layer being provided with a first via hole for exposing the drain electrode;

a pixel electrode layer disposed on the surface of the planarization layer away from the substrate, the pixel electrode layer covering the first via hole and being in contact with the drain electrode; and

a photoresist layer covering the pixel electrode layer, and the photoresist layer filling the first via hole which is covered with the pixel electrode layer;

wherein a common electrode layer is disposed on the planarization layer and a passivation layer is disposed on and covers the common electrode layer, wherein the passivation layer has a part extending into the first via hole formed in the planarization, the first via hole being delimited by a sidewall that is formed of a part of the planarization layer, wherein the part of the passivation layer that extends into the first via hole covers the sidewall of the first via hole and directly contacts the part of the planarization layer that defines the sidewall;

wherein the pixel electrode layer is disposed on the passivation layer and covers the passivation layer, and the pixel electrode layer is in contact with the drain electrode through the first via hole; and

wherein the photoresist layer has a planar top surface that is distant from the pixel electrode layer, the planar top surface being extended to completely cover the thin-film transistor and also extended such that a photoresist column is formed on and integrally connected with the planar top surface of the photoresist layer.

2. The array substrate according to claim 1, wherein the photoresist column is used to support the display panel.

3. The array substrate according to claim 2, wherein the thin-film transistor comprises a light shielding layer disposed on the substrate, a buffer layer covering the light shielding layer, a polysilicon layer disposed on the buffer layer, and a dielectric insulating layer covering the polysilicon layer, and the dielectric insulating layer is provided with a second via hole and a third via hole, which are arranged at intervals and expose a portion of the surface of the polysilicon layer, wherein the thin-film transistor further comprises a source electrode, and the source electrode and the drain electrode are disposed on the dielectric insulating layer, and the drain electrode is in contact with the polysilicon layer through the second via hole, and the source electrode is in contact with the polysilicon layer through the third via hole, wherein the planarization layer is disposed on the source electrode, the drain electrode and the dielectric insulating layer.

4. The array substrate according to claim 3, wherein the dielectric insulating layer comprises an insulating layer and a dielectric layer stacked on the insulating layer, wherein the thin-film transistor comprises a gate electrode, the gate electrode is disposed on the insulating layer, and the dielectric layer covers the gate electrode.

5. A display panel, comprising the array substrate according to claim 1.

6. The display panel according to claim 5, wherein the photoresist column is used to support the display panel.

7. The display panel according to claim 6, wherein the thin-film transistor comprises a light shielding layer disposed on the substrate, a buffer layer covering the light shielding layer, a polysilicon layer disposed on the buffer layer, and a dielectric insulating layer covering the polysilicon layer, and the dielectric insulating layer is provided with a second via hole and a third via hole, which are arranged at intervals and expose a portion of the surface of the polysilicon layer, wherein the thin-film transistor further comprises a source electrode, and the source electrode and the drain electrode are disposed on the dielectric insulating layer, and the drain electrode is in contact with the polysilicon layer through the second via hole, and the source electrode is in contact with the polysilicon layer through the third via hole, wherein the planarization layer is disposed on the source electrode, the drain electrode and the dielectric insulating layer.

8. The display panel according to claim 7, wherein the dielectric insulating layer comprises an insulating layer and a dielectric layer stacked on the insulating layer, wherein the thin-film transistor comprises a gate electrode, the gate electrode is disposed on the insulating layer, and the dielectric layer covers the gate electrode.

9. A method for manufacturing an array substrate, comprising:

providing a substrate;

forming a thin-film transistor on the substrate;

forming a planarization layer on the thin-film transistor;

forming a first via hole in the planarization layer, the first via hole exposing a drain electrode of the thin-film transistor;

forming a pixel electrode layer on the surface of the planarization layer away from the substrate, the pixel electrode layer covering the first via hole and being in contact with the drain electrode; and

forming a photoresist layer on the pixel electrode layer, the photoresist layer covering the pixel electrode layer, and the photoresist layer filling the first via hole which is covered with the pixel electrode layer;

wherein the step of forming a pixel electrode layer on the surface of the planarization layer away from the substrate comprises;

forming a common electrode layer on the planarization layer; and

forming a passivation layer on the common electrode layer, such that the passivation layer covers the common electrode layer, wherein the passivation layer has a part extending into the first via hole formed in the planarization, the first via hole being delimited by a sidewall that is formed of a part of the planarization layer, wherein the part of the passivation layer that extends into the first via hole covers the sidewall of the first via hole and directly contacts the part of the planarization layer that defines the sidewall;

wherein the pixel electrode layer is formed on the passivation layer and covers the passivation layer, and the pixel electrode is in contact with the drain electrode through the first via hole;

wherein after the step of forming a photoresist layer on the pixel electrode layer, the method further comprises forming a photoresist column on the photoresist layer; and

wherein the photoresist layer has a planar top surface that is distant from the pixel electrode layer, the planar top surface being extended to completely cover the thin-film transistor and also extended such that the photoresist column is formed on and integrally connected with the planar top surface of the photoresist layer.

10. The method for manufacturing an array substrate according to claim 9, wherein the step of forming a thin-film transistor on the substrate comprises:

forming a light shielding layer on the substrate;

forming a buffer layer on the light shielding layer, and buffer layer covering the light shielding layer;

forming a polysilicon layer on the buffer layer;

forming a dielectric insulating layer on the polysilicon layer, the dielectric insulating layer covering the polysilicon layer;

forming a second via hole and a third via hole in the dielectric insulating layer, the second via hole and the third via hole being arranged at intervals and exposing a portion of the surface of the polysilicon layer;

forming a source electrode and a drain electrode on the dielectric insulating layer, the drain electrode being in contact with the polysilicon layer through the second via hole, and the source electrode being in contact with the polysilicon layer through the third via hole.