Dual-gate PMOS field effect transistor with InGaAs channel

• US 10,644,100 B2
• Filed: 12/28/2016
• Issued: 05/05/2020
• Est. Priority Date: 10/12/2016
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences (Chinese Academy of Sciences)
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences (Chinese Academy of Sciences)
• Inventors: Wang, Shengkai, Liu, Honggang, Sun, Bing, Chang, Hudong
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US15/539,478
• Publication Number:
  US 20190229182A1
• Time in Patent Office: 1,224 Days
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate

Abstract

The present disclosure relates to the field of semiconductor Integrated Circuit (IC) manufacture, and provides an InGaAs-based double-gate PMOS Field Effect Transistor (FET). The FET includes a bottom gate electrode, a bottom gate dielectric layer, a bottom gate interface control layer, an InGaAs channel layer, an upper interface control layer, a highly doped P-type GaAs layer, an ohmic contact layer, source/drain metal electrodes, a top gate dielectric layer and a top gate electrode. The source/drain metal electrodes are located on opposite sides of the ohmic contact layer. A gate trench structure is etched to an upper surface of the interface control layer between the source and drain metal electrodes. The top gate dielectric layer uniformly covers an inner surface of the gate trench structure, and the top gate electrode is provided on the top gate dielectric layer. The present disclosure provides a PMOS FET with better gate control functionality and a low interface density with the double-gate structure and interface control layer design, in order to meet the requirements of high-performance PMOS transistors.

Claims

1. A Field Effect Transistor (FET), comprising:

a bottom gate structure comprising a bottom gate electrode and a bottom gate dielectric layer;

an InGaAs channel layer;

a top gate structure comprising a top gate electrode and a top gate dielectric layer different from the bottom gate electrode and bottom gate dielectric layer; and

a lower interface control layer and an upper interface control layer,

wherein the bottom gate dielectric layer is disposed between the bottom gate electrode and the InGaAs channel layer, and the top gate dielectric layer is disposed between the top gate electrode and the InGaAs channel layer,

wherein the lower interface control layer is disposed between the bottom gate dielectric layer and the InGaAs channel layer, and the upper interface control layer is disposed between the top gate structure and the InGaAs channel layer, and

wherein the upper interface control layer and the lower interface control layer each have a bandgap greater than that of the InGaAs channel layer, and the upper interface control layer and the lower interface control layer each has a first type of quantum well band alignment relationship with the InGaAs channel layer, and

wherein the upper interface control layer and the lower interface control layer each have a thickness in a range between a single atomic layer and 20 nm.

2. The FET according to claim 1, wherein the InGaAs channel layer has a thickness of 1 to 20 nm, with a low In composition between 0.2 and 0.4.

3. The FET according to claim 1, wherein holes in the InGaAs channel layer have a quantum confinement effect.

4. The FET according to claim 1, wherein the bottom gate electrode comprises an electrode metal layer and a work function layer.

5. The FET according to claim 1, further comprising:

highly doped P-type GaAs layers disposed on the upper interface control layer on opposite sides of the top gate structure, respectively,

ohmic contact layers disposed on the highly doped P-type GaAs layers, respectively, and source/drain metal electrodes disposed on the ohmic contact layers, respectively.

6. The FET according to claim 5, wherein each of the ohmic contact layer comprises a heavily doped InGaAs material with a doping concentration greater than 1e¹⁹ cm⁻

3.

7. The FET according to claim 5, wherein each of the highly doped P-type GaAs layer has a doping concentration greater than 1e¹⁸ cm⁻

3.

8. The FET according to claim 5, wherein each of the upper interface control layer and the lower interface control layer has a lattice having a matching or pseudo-mating relationship with that of the InGaAs channel layer.

9. The FET according to claim 5, wherein the top gate dielectric layer uniformly extends on a surface of the upper interface control layer between the highly doped P-type GaAs layers opposite to each other, surfaces of the highly doped P-type GaAs layers facing each other, and surfaces of the ohmic contact layers facing each other.

10. The FET according to claim 1, wherein the top gate electrode comprises an electrode metal layer and a work function layer.

11. The FET according to claim 1, wherein the top gate dielectric layer and the bottom gate dielectric layer each have a dielectric constant K greater than 8.

12. The FET according to claim 11, wherein the top gate dielectric layer and the bottom gate dielectric layer each comprises a material selected from oxide, nitride, oxynitride, any mixture thereof, or any combination of multiple layers thereof.

13. A Field Effect Transistor (FET), comprising:

a bottom gate structure comprising a bottom gate electrode and a bottom gate dielectric layer;

an InGaAs channel layer having a thickness of 1 to 20 nm,

a top gate structure comprising a top gate electrode and top gate dielectric layer, wherein the top gate electrode and top gate dielectric layer are different from the bottom gate electrode and bottom gate dielectric layer; and

a lower interface control layer and an upper interface control layer wherein the upper interface control layer and the lower interface control layer each have a thickness in a range between a single atomic layer and 20 nm and wherein the upper interface control layer and the lower interface control layer both have a lattice having a matching or pseudo-mating relationship with that of the InGaAs channel layer,

wherein the bottom gate dielectric layer is disposed between the bottom gate electrode and the InGaAs channel layer, and the top gate dielectric layer is disposed between the top gate electrode and the InGaAs channel layer,

wherein the lower interface control layer is disposed between the bottom gate dielectric layer and the InGaAs channel layer, and the upper interface control layer is disposed between the top gate dielectric layer and the InGaAs channel layer, and

wherein the upper interface control layer and the lower interface control layer each have a bandgap greater than that of the InGaAs channel layer, and the upper interface control layer and the lower interface control layer each has a first type of quantum well band alignment relationship with the InGaAs channel layer.