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Dual-gate PMOS field effect transistor with InGaAs channel

  • US 10,644,100 B2
  • Filed: 12/28/2016
  • Issued: 05/05/2020
  • Est. Priority Date: 10/12/2016
  • Status: Active Grant
First Claim
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1. A Field Effect Transistor (FET), comprising:

  • a bottom gate structure comprising a bottom gate electrode and a bottom gate dielectric layer;

    an InGaAs channel layer;

    a top gate structure comprising a top gate electrode and a top gate dielectric layer different from the bottom gate electrode and bottom gate dielectric layer; and

    a lower interface control layer and an upper interface control layer,wherein the bottom gate dielectric layer is disposed between the bottom gate electrode and the InGaAs channel layer, and the top gate dielectric layer is disposed between the top gate electrode and the InGaAs channel layer,wherein the lower interface control layer is disposed between the bottom gate dielectric layer and the InGaAs channel layer, and the upper interface control layer is disposed between the top gate structure and the InGaAs channel layer, andwherein the upper interface control layer and the lower interface control layer each have a bandgap greater than that of the InGaAs channel layer, and the upper interface control layer and the lower interface control layer each has a first type of quantum well band alignment relationship with the InGaAs channel layer, andwherein the upper interface control layer and the lower interface control layer each have a thickness in a range between a single atomic layer and 20 nm.

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