SGT superjunction MOSFET structure

• US 10,644,102 B2
• Filed: 12/28/2017
• Issued: 05/05/2020
• Est. Priority Date: 12/28/2017
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Padmanabhan, Karthik, Guan, Lingpeng, Bobde, Madhur, Wang, Jian, Zhang, Lei
• Primary Examiner(s): Clark, Jasmine J
• Application Number:
  US15/856,828
• Publication Number:
  US 20190206988A1
• Time in Patent Office: 859 Days
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a combination of shielded trench gate structure and a superjunction structure within an epitaxial layer including alternating n-doped and p-doped columns in an a drift region. In one example the gate trenches are formed in and over n-doped columns that have an extra charge region near and adjacent to the lower portion of the corresponding gate trench. The extra charge is balanced due to the shield electrodes in the gate trenches.

Claims

1. A metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising:

a drift region of a first conductivity type provided on top of a heavily doped substrate of a same conductivity type;

a body region of a second conductivity type that is opposite to the first conductivity type provided above the drift region;

a plurality of trenches provided in the body region and extending into the drift region;

a heavily doped source region of the first conductivity type provided in the body region; and

a superjunction structure provided in the drift region including alternating first doped columns of the first conductivity type and second doped columns of the second conductivity type arranged in parallel, wherein each of the second doped columns is provided between two adjacent trenches, wherein each of the first doped columns has an extra charge density region near and adjacent to a corresponding one of the plurality of trenches, wherein the alternating first doped columns and the second doped columns are in substantial charge balance in the drift region.

2. The device of claim 1, wherein each of the plurality of trenches is centered at a top portion of a first doped column and between two adjacent second doped columns.

3. The device of claim 1, wherein each of the plurality of trenches has a bottom that terminates in the extra charge density region.

4. The device of claim 1, wherein each of the plurality of trenches is no wider than a width of a corresponding one of the first doped columns.

5. The device of claim 1, wherein the first doped columns have a varying doping profile across the drift region, wherein a region above a bottom region and below the extra charge density region has a net charge density lower than a net charge density in the bottom region.

6. The device of claim 1, wherein the extra charge density region near and adjacent to a lower portion of the corresponding one of the plurality of trenches has a largest doping concentration comparing to other regions in the first doped columns.

7. The device of claim 1, wherein each trench of the plurality of trenches is lined with a dielectric material has a gate electrode in the upper portion and a shield electrode in the lower portion.

8. The device of claim 1, wherein each trench of the plurality of trenches is lined with a dielectric material has a gate electrode in the upper portion and a dielectric material filling a lower portion of each of the plurality of trenches.

9. The device of claim 1, wherein the extra charge density region has about 20% to 50% higher charge density than other portions of the first doped columns.

10. The device of claim 1, wherein a ratio of gate trench width to superjunction pitch is about 0.175.

11. A metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising:

a drift region of the a conductivity type provided on top of a heavily doped layer of a same conductivity type;

a body region of a second conductivity type that is opposite to the first conductivity type provided above the drift region;

a plurality of trenches provided in the body region and extending into the drift region;

a heavily doped source region of the first conductivity type provided in the body region; and

a superjunction structure provided in the drift region including alternating first doped columns of the first conductivity type and second doped columns of the second conductivity type arranged in parallel, wherein each of the second doped columns is provided between two adjacent trenches, wherein each of the first doped columns and the second doped columns extends below a bottom of the trenches, wherein the alternating first doped columns and the second doped columns are in substantial charge balance in the drift region.

12. The device of claim 11, wherein each of the plurality of trenches is centered at a top portion of a first doped column and between two adjacent second doped columns.

13. The device of claim 12, wherein each of the plurality of trenches has a bottom terminated in a top portion of a corresponding one of the first doped column.

14. The device of claim 11, wherein each trench of the plurality of trenches is narrower than a width of a corresponding one of the first doped columns.

15. The device of claim 11, wherein the first doped columns have a varying doping profile across the drift region, wherein a region above a bottom region and below a top region has a net charge density lower than a net charge density in the bottom region.

16. The device of claim 11, wherein a top region in the first doped columns near and adjacent to a lower portion of the corresponding one of the plurality of trenches has a largest net charge doping concentration comparing to other regions in the first doped columns.

17. The device of claim 11, wherein each trench of the plurality of trenches is lined with a dielectric material has a gate electrode in the upper portion and a shield electrode in the lower portion.

18. The device of claim 11, wherein each trench of the plurality of trenches is lined with a dielectric material has a gate electrode in the upper portion and a dielectric material filling a lower portion of each of the plurality of trenches.

19. A superjunction semiconductor device, comprising:

a drift region of a first conductivity type provided on top of a heavily doped layer of a same conductivity type;

a body region of a second conductivity type that is opposite to the first conductivity type provided above the drift region; and

a superjunction structure provided in the drift region including alternating first doped columns of the first conductivity type and second doped columns of the second conductivity type arranged in parallel, wherein the first doped columns have a varying doping profile across the drift region, wherein a middle region above a bottom region and below an upper region has a net charge density lower than a net charge density in the bottom region and the upper region, wherein the alternating first doped columns and the second doped columns are in substantial charge balance in the drift region.

20. The device of claim 19, wherein each of the bottom region, the middle region and the upper region in each of the first doped columns comprises a plurality of epitaxial layers doped with the first conductivity.

21. The device of claim 20, wherein each of the plurality of epitaxial layers doped with the first conductivity in the middle region has a dose lower than a dose in each epitaxial layer in the bottom region and the upper region.

22. The device of claim 19, wherein each of the first doped columns further comprising a top region above the upper region.

23. The device of claim 22, wherein each of the bottom region, the middle region, the upper region and the top region in each of the first doped columns comprises a plurality of epitaxial layers doped with the first conductivity, wherein each of the plurality of epitaxial layers doped with the first conductivity in the top region has a dose higher than a dose in each epitaxial layer in the bottom region, the middle region and the upper region.

24. The device of claim 19, wherein each of the first doped columns further comprises a top region above the upper region, wherein each of the plurality of epitaxial layers doped with the first conductivity in the top region has a dose higher than a dose in each epitaxial layer in the bottom region, the middle region and the upper region.

25. A superjunction semiconductor device, comprising:

a drift region comprising a superjunction structure provided in the drift region including alternating first doped columns of a first conductivity type and second doped columns of the second conductivity type arranged in parallel, wherein the first doped columns comprising a plurality of epitaxial layers doped with the first conductivity having a varying doping profile across the drift region, wherein a middle region above a bottom region and below an upper region has a dose for each epitaxial layer lower than a dose in each of epitaxial layer in the bottom region and in the upper region, wherein the alternating first doped columns and the second doped columns are in substantial charge balance in the drift region.