Systems, methods and devices for isolation for subfin leakage

• US 10,644,112 B2
• Filed: 09/28/2016
• Issued: 05/05/2020
• Est. Priority Date: 09/28/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chu-Kung, Benjamin, Le, Van, Sung, Seung Hoon, Kavalieros, Jack, Agrawal, Ashish, Kennel, Harold, Chouksey, Siddharth, Murthy, Anand, Ghani, Tahir, Glass, Glenn, Huang, Cheng-Ying
• Primary Examiner(s): Nikmanesh, Seahvosh
• Application Number:
  US16/326,890
• Publication Number:
  US 20190189749A1
• Time in Patent Office: 1,315 Days
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.

Claims

1. An apparatus comprising:

a substrate layer comprising silicon;

a transition layer comprising silicon and germanium coupled to the substrate layer;

a germanium layer coupled to the transition layer;

a transistor gate coupled to the germanium layer; and

an implanted layer comprising an implant causing exposed portions of the germanium layer to become resistive, and

wherein an area underneath the transistor gate remains without implant.

2. The apparatus of claim 1, wherein the implant comprises oxygen.

3. The apparatus of claim 1, wherein the implant comprises silicon, germanium, carbon or nitrogen.

4. The apparatus of claim 1, wherein the implant is performed as a vertical implantation.

5. The apparatus of claim 1, wherein the implant causes the implanted layer to become amorphized.

6. The apparatus of claim 5, wherein the implanted layer recrystallizes at a higher temperature than the germanium layer.

7. The apparatus of claim 5, wherein the germanium recrystallizes at a lower temperature than a silicon-germanium subfin.

8. The apparatus of any of claim 1, wherein the implant reduces subfin leakage.

9. The apparatus of any of claim 1, further comprising a crystalline germanium source and a crystalline germanium drain coupled to the implanted layer.

10. The apparatus of any of claim 1, wherein the apparatus forms part of a processor.

11. A method for constructing an integrated circuit gate with reduced parasitic subfin leakage, the method comprising:

providing a substrate comprising a silicon layer, a germanium layer and a transition layer comprising silicon and germanium coupled between the silicon layer and the germanium layer;

exposing the germanium layer;

disposing a gate on the germanium layer; and

performing implantation to create a resistive area, wherein an area underneath the gate remains without implant.

12. The method of claim 11, further comprising performing an undercuttage under the gate.

13. The method of claim 11, further comprising performing an anneal to recrystallize the germanium layer.

14. The apparatus of claim 11, wherein performing implantation further comprises performing a halo-shaped implantation around the gate on the germanium layer.

15. The method of claim 11, wherein performing implantation further comprises creating a local silicon on insulator area.

16. A computing device comprising:

a processor mounted on a substrate;

a memory unit capable of storing data;

a graphics processing unit;

an antenna within the computing device;

a display on the computing device;

a battery within the computing device;

a power amplifier within the processor; and

a voltage regulator within the processor;

wherein the processor comprises;

a substrate layer comprising silicon;

a transition layer comprising silicon and germanium coupled to the substrate layer;

a germanium layer coupled to the transition layer;

a transistor gate coupled to the germanium layer; and

an implanted layer comprising an implant causing exposed portions of the germanium layer to become resistive, and

wherein an area underneath the transistor gate remains without implant.

17. The computing device of claim 16, wherein the implanted layer comprises amorphous silicon-germanium or oxidized silicon-germanium.

18. The computing device of claim 16, wherein a shallow trench isolation (STI) interface is achieved through the implant without a liner.

19. The computing device of claim 16, wherein the implanted layer is more resistive after the implant than before the implant.