MOS-varactor design to improve tuning efficiency

• US 10,644,124 B2
• Filed: 12/10/2018
• Issued: 05/05/2020
• Est. Priority Date: 07/01/2016
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation), Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Original Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: Li, Yong
• Primary Examiner(s): Kim, Tong-Ho
• Application Number:
  US16/214,201
• Publication Number:
  US 20190109201A1
• Time in Patent Office: 512 Days
• Field of Search: 257312
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66174 Capacitors with PN or Schottky junction, e.g. varactors capacitors with PN junction combined with MOS control H01L29/66189
• CPC Class Codes: H01L 29/93 Variable capacitance diodes, e.g. varactors

Abstract

A gate stack structure for a MOS varactor includes a substrate including a channel region, a high-k dielectric layer on the channel region of the substrate, a P-type work function adjustment layer on the high-k dielectric layer, an N-type work function adjustment layer on the P-type work function adjustment layer, and a metal gate on the N-type work function adjustment layer. The P-type work function adjustment layer includes a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion. The gate stack structure in the MOS varactor can increase the tuning range of the MOS varactor.

Claims

1. A method for manufacturing a gate stack structure for a MOS varactor, the method comprising:

providing a substrate including a channel region;

forming a high-k dielectric layer on the channel region;

forming a P-type work function layer on the high-k dielectric layer, the P-type work function adjustment layer including a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion;

forming an N-type work function adjustment layer on the P-type work function adjustment layer; and

forming a metal gate on the N-type work function adjustment layer.

2. The method of claim 1, wherein forming the P-type work function layer comprises:

forming a first TiN layer on the high-k dielectric layer;

removing a portion of the first TiN layer to expose a portion of the high-k dielectric layer;

forming a second TiN layer on a remaining portion of the first TiN layer and on the exposed portion of the high-k dielectric layer.

3. The method of claim 1, wherein forming the P-type work function layer comprises:

forming a first TiN layer on the high-k dielectric layer;

forming a TaN layer on the first TiN layer;

removing a portion of the TaN layer and a portion of the first TiN layer to expose a portion of the high-k dielectric layer;

forming a second TiN layer on a remaining portion of the TaN layer and on the exposed portion of the high-k dielectric layer.

4. The method of claim 1, wherein forming the P-type work function layer comprises:

forming a first TiN layer on the high-k dielectric layer;

removing a portion of the first TiN layer to expose a portion of the high-k dielectric layer;

forming a second TiN layer on a remaining portion of the first TiN layer and on the exposed portion of the high-k dielectric layer; and

forming a TaN layer on the second TiN layer.

5. The method of claim 1, further comprising:

forming a barrier layer on the N-type work function adjustment layer.

6. The method of claim 1, wherein the N-type work function adjustment layer comprises TiAl, TiCAl, TiNAl, or TiSiAl.

7. The method of claim 1, wherein a ratio of a length of the first portion to a length of the second portion of the P-type work function adjustment layer is in a range between 1/9 and 9.