Method and apparatus for MOS device with doped region

• US 10,644,132 B2
• Filed: 02/10/2017
• Issued: 05/05/2020
• Est. Priority Date: 02/27/2014
• Status: Active Grant

• Current Assignee: Vanguard International Semiconductor Corporation
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Lee, Tsung-Hsiung, Lin, Shin-Cheng
• Primary Examiner(s): Campbell, Shaun M
• Assistant Examiner(s): Cieslewicz, Aneta B
• Application Number:
  US15/430,097
• Publication Number:
  US 20170213898A1
• Time in Patent Office: 1,180 Days
• Field of Search: None
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a first doped well, having a first conductivity type, in a first semiconductor layer having a second conductivity type;

forming a second semiconductor layer having the second conductivity type on the first semiconductor layer;

forming a second doped well of the first conductivity type in the second semiconductor layer;

forming a first doped region having the second conductivity type in the second doped well;

forming a second doped region having the first conductivity type in the second doped well, the second doped region disposed above the first doped region;

forming a third doped region having the first conductivity type in the second semiconductor layer, the third doped region being disposed apart from the second doped well;

forming a fourth doped region in the second semiconductor layer after forming the third doped region, the fourth doped region having the second conductivity type, the fourth doped region being formed between the second doped well and the third doped region;

forming a fifth doped region having the second conductivity type in the second semiconductor layer, the fifth doped region being disposed apart from the second doped well and the fourth doped region;

forming a first insulator on the fourth doped region;

forming a conductive member on the insulator;

forming a source region in the third doped region;

forming a drain region in the second doped well; and

forming a body region in the second semiconductor layer.