III-V finfet transistor with V-groove S/D profile for improved access resistance

• US 10,644,137 B2
• Filed: 07/02/2016
• Issued: 05/05/2020
• Est. Priority Date: 07/02/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rachmady, Willy, Metz, Matthew V., Dewey, Gilbert, Ma, Sean T., Mohapatra, Chandra S., Gardner, Sanaz K., Kavalieros, Jack T., Murthy, Anand S., Ghani, Tahir
• Primary Examiner(s): Spalla, David C
• Application Number:
  US16/099,418
• Publication Number:
  US 20190148512A1
• Time in Patent Office: 1,403 Days
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

An apparatus including a transistor device including a body including a channel region between a source region and a drain region; and a gate stack on the body in the channel region, wherein at least one of the source region and the drain region of the body include a contact surface between opposing sidewalls and the contact surface includes a profile such that a height dimension of the contact surface is greater at the sidewalls than at a point between the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body dimension defining a channel region between a source region and a drain region; forming a groove in the body in at least one of the source region and the drain region; and forming a gate stack on the body in the channel region.

Claims

1. An apparatus comprising:

a transistor device disposed on a surface of a circuit substrate, the transistor device comprising;

a body comprising a height dimension, opposing sidewalls defining a width dimension and a length dimension defining a channel region between a source region and a drain region;

a gate stack on the body in the channel region, wherein at least one of the source region and the drain region of the body comprise a contact surface between the opposing sidewalls and the contact surface comprises a profile such that a height dimension of the contact surface is greater at the sidewalls than at a point between the sidewalls; and

a metal contact on the contact surface of the at least one of the source region and the drain region of the body.

2. The apparatus of claim 1, wherein the contact surface defines a groove between the opposing sidewalls such that a surface area of the contact surface between the sidewalls of each of the source region and the drain region of the body is greater than the surface area defined by the width dimension of the body without the groove.

3. The apparatus of claim 2, wherein the groove comprises a shape of the letter V.

4. The apparatus of claim 1, wherein the channel region of the body comprises a Group III to Group V compound semiconductor material.

5. The apparatus of claim 4, wherein the channel region of the body comprises indium-gallium-arsenide.

6. The apparatus of claim 1, wherein the body is disposed on a buffer material.

7. The apparatus of claim 6, wherein the buffer material comprises germanium or a Group III to Group V compound semiconductor material that is different than the channel material.

8. The apparatus of claim 1, wherein the gate stack comprises a gate electrode and a gate dielectric material wherein the gate dielectric material is disposed between the channel region and the gate electrode.

9. The apparatus of claim 7, wherein a profile of the body in the channel region is different than the profile of the body in the at least one of the source region and the drain region.

10. A method comprising:

forming a transistor device body on a circuit substrate, the transistor device body comprising a height dimension, opposing sidewalls defining a width dimension and a length dimension defining a channel region between a source region and a drain region;

forming a groove in the body in at least one of the source region and the drain region;

forming a gate stack on the body in the channel region; and

forming a metal contact on the groove in the body in the at least one of the source region and the drain region.

11. The method of claim 10, wherein forming a groove comprises etching the body in the source region and the drain region.

12. The method of claim 10, wherein the groove comprises a shape of the letter V.

13. The method of claim 10, wherein the body comprises a Group III to Group V compound semiconductor material.

14. The method of claim 13, wherein the body comprises indium-gallium-arsenide.

15. The method of claim 10, wherein the body is formed on a buffer material.

16. The method of claim 10, wherein a profile of the body in the channel region is different than a profile of the body in the at least one of the source region and the drain region.

17. A system comprising:

a computer comprising a processor coupled to a printed circuit board, the processor comprising transistor device circuitry in which a non-planar transistor device comprises

(1) a body comprising a height dimension, opposing sidewalls defining a width dimension comprising a contact surface between the opposing sidewalls and a length dimension defining a channel region between a source region and a drain region, wherein the contact surface of at least one of the source region and the drain region comprises a groove;

(2) a gate stack on the contact surface of the channel region; and

(3) a metal contact on the contact surface of the at least one of the source region and the drain region of the body.

18. The system of claim 17, wherein the body of the transistor device is a Group III to Group V compound semiconductor material.

19. The system of claim 18, wherein the body comprises indium-gallium-arsenide.

20. The system of claim 17, wherein the groove comprises a shape of the letter V.

21. The system of claim 20, wherein a profile of the body in the channel region is different than a profile of the body in the at least one of the source region and the drain region.