III-V finfet transistor with V-groove S/D profile for improved access resistance
First Claim
1. An apparatus comprising:
- a transistor device disposed on a surface of a circuit substrate, the transistor device comprising;
a body comprising a height dimension, opposing sidewalls defining a width dimension and a length dimension defining a channel region between a source region and a drain region;
a gate stack on the body in the channel region, wherein at least one of the source region and the drain region of the body comprise a contact surface between the opposing sidewalls and the contact surface comprises a profile such that a height dimension of the contact surface is greater at the sidewalls than at a point between the sidewalls; and
a metal contact on the contact surface of the at least one of the source region and the drain region of the body.
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Abstract
An apparatus including a transistor device including a body including a channel region between a source region and a drain region; and a gate stack on the body in the channel region, wherein at least one of the source region and the drain region of the body include a contact surface between opposing sidewalls and the contact surface includes a profile such that a height dimension of the contact surface is greater at the sidewalls than at a point between the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body dimension defining a channel region between a source region and a drain region; forming a groove in the body in at least one of the source region and the drain region; and forming a gate stack on the body in the channel region.
11 Citations
21 Claims
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1. An apparatus comprising:
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a transistor device disposed on a surface of a circuit substrate, the transistor device comprising; a body comprising a height dimension, opposing sidewalls defining a width dimension and a length dimension defining a channel region between a source region and a drain region; a gate stack on the body in the channel region, wherein at least one of the source region and the drain region of the body comprise a contact surface between the opposing sidewalls and the contact surface comprises a profile such that a height dimension of the contact surface is greater at the sidewalls than at a point between the sidewalls; and a metal contact on the contact surface of the at least one of the source region and the drain region of the body. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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forming a transistor device body on a circuit substrate, the transistor device body comprising a height dimension, opposing sidewalls defining a width dimension and a length dimension defining a channel region between a source region and a drain region; forming a groove in the body in at least one of the source region and the drain region; forming a gate stack on the body in the channel region; and forming a metal contact on the groove in the body in the at least one of the source region and the drain region. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A system comprising:
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a computer comprising a processor coupled to a printed circuit board, the processor comprising transistor device circuitry in which a non-planar transistor device comprises (1) a body comprising a height dimension, opposing sidewalls defining a width dimension comprising a contact surface between the opposing sidewalls and a length dimension defining a channel region between a source region and a drain region, wherein the contact surface of at least one of the source region and the drain region comprises a groove; (2) a gate stack on the contact surface of the channel region; and (3) a metal contact on the contact surface of the at least one of the source region and the drain region of the body. - View Dependent Claims (18, 19, 20, 21)
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Specification