Integrated circuit die having back-end-of-line transistors
First Claim
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1. An integrated circuit die, comprising:
- a front-end-of-line (FEOL) portion including a silicon layer having a plurality of transistors, and an insulating layer over the silicon layer; and
a back-end-of-line (BEOL) portion mounted on the insulating layer, the BEOL portion including a non-planar transistor havingan amorphous oxide semiconductor (AOS) channel extending axially from a first end to a second end, anda gate module extending transversely around the AOS channel at an axial location between a source module at the first end and a drain module at the second end, wherein the AOS channel includes an AOS layer between an upper dielectric layer and a lower dielectric layer, and wherein the upper dielectric layer is between an upper metal gate layer and the AOS layer, and the lower dielectric layer is between a lower metal gate layer and the AOS layer.
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Abstract
Integrated circuit dies having multi-gate, non-planar transistors built into a back-end-of-line portion of the die are described. In an example, non-planar transistors include an amorphous oxide semiconductor (AOS) channel extending between a source module and a drain module. A gate module may extend around the AOS channel to control electrical current flow between the source module and the drain module. The AOS channel may include an AOS layer having indium gallium zinc oxide.
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Citations
17 Claims
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1. An integrated circuit die, comprising:
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a front-end-of-line (FEOL) portion including a silicon layer having a plurality of transistors, and an insulating layer over the silicon layer; and a back-end-of-line (BEOL) portion mounted on the insulating layer, the BEOL portion including a non-planar transistor having an amorphous oxide semiconductor (AOS) channel extending axially from a first end to a second end, and a gate module extending transversely around the AOS channel at an axial location between a source module at the first end and a drain module at the second end, wherein the AOS channel includes an AOS layer between an upper dielectric layer and a lower dielectric layer, and wherein the upper dielectric layer is between an upper metal gate layer and the AOS layer, and the lower dielectric layer is between a lower metal gate layer and the AOS layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit package, comprising:
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a package substrate; and an integrated circuit die mounted on the package substrate, wherein the integrated circuit die includes a front-end-of-line (FEOL) portion including a silicon layer having a plurality of transistors, and an insulating layer over the silicon layer, and a back-end-of-line (BEOL) portion mounted on the insulating layer, the BEOL portion including a non-planar transistor having a stack of amorphous oxide semiconductor (AOS) channels extending axially from a first end to a second end, and a gate module extending transversely around the stack of AOS channels at an axial location between a source module at the first end and a drain module at the second end, wherein the stack of AOS channels includes a plurality of AOS layers between respective upper dielectric layers and lower dielectric layers, and wherein the respective upper dielectric layers are between respective upper metal gate layers and the respective AOS layer, and the respective lower dielectric layer is between a respective lower metal gate layer and the respective AOS layer. - View Dependent Claims (10, 11, 12, 13)
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14. A method, comprising:
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forming an amorphous oxide semiconductor (AOS) channel on a front-end-of-line (FEOL) portion of an integrated circuit die having a plurality of transistors, wherein the AOS channel extends axially from a first end to a second end; forming a gate module over the AOS channel, wherein the gate module extends around the AOS channel axially between the first end and the second end; forming a source module over the first end of the AOS channel; and forming a drain module over the second end of the AOS channel, wherein forming the AOS channel includes sequentially depositing a lower metal gate layer, a lower dielectric layer, an AOS layer, an upper dielectric layer, and an upper metal gate layer on an insulating layer of the FEOL portion. - View Dependent Claims (15, 16, 17)
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Specification