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Integrated circuit die having back-end-of-line transistors

  • US 10,644,140 B2
  • Filed: 06/30/2016
  • Issued: 05/05/2020
  • Est. Priority Date: 06/30/2016
  • Status: Active Grant
First Claim
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1. An integrated circuit die, comprising:

  • a front-end-of-line (FEOL) portion including a silicon layer having a plurality of transistors, and an insulating layer over the silicon layer; and

    a back-end-of-line (BEOL) portion mounted on the insulating layer, the BEOL portion including a non-planar transistor havingan amorphous oxide semiconductor (AOS) channel extending axially from a first end to a second end, anda gate module extending transversely around the AOS channel at an axial location between a source module at the first end and a drain module at the second end, wherein the AOS channel includes an AOS layer between an upper dielectric layer and a lower dielectric layer, and wherein the upper dielectric layer is between an upper metal gate layer and the AOS layer, and the lower dielectric layer is between a lower metal gate layer and the AOS layer.

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