Growth of cubic crystalline phase structure on silicon substrates and devices comprising the cubic crystalline phase structure

• US 10,644,144 B2
• Filed: 11/14/2018
• Issued: 05/05/2020
• Est. Priority Date: 05/04/2012
• Status: Active Grant

• Current Assignee: Rensselaer Polytechnic Institute
• Original Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Inventors: Brueck, Steven R. J., Lee, Seung-Chang, Wetzel, Christian, Durniak, Mark
• Primary Examiner(s): Chin, Edward
• Application Number:
  US16/191,197
• Publication Number:
  US 20190103481A1
• Time in Patent Office: 538 Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02587 Structure
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/7806 involving the separation of the active layers from a substrate
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66462 : with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7787 : with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 33/007 : comprising nitride compounds
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/24 : of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/32 : containing nitrogen
• CPC Class Codes: H01S 5/021 : Silicon based substrates
• CPC Class Codes: H01S 5/22 : having a ridge or stripe structure
• CPC Class Codes: H01S 5/227 : Buried mesa structure ; Striped active layer
• CPC Class Codes: H01S 5/3203 : on non-planar substrates to create thickness or compositional variations
• CPC Class Codes: H01S 5/34333 : with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser

Abstract

A transistor comprises a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase structure positioned on a hexagonal crystalline phase layer having a first region and a second region, the cubic crystalline phase structure being positioned between the first region and the second region of the hexagonal crystalline phase layer. A source region and a drain region are both positioned in the Group III/V compound semiconductor material. A channel region is in the Group III/V compound semiconductor material. A gate is over the channel region. An optional backside contact can also be formed. A source contact and electrode are positioned to provide electrical contact to the source region. A drain contact and electrode are positioned to provide electrical contact to the drain region. Methods of forming transistors are also disclosed.

Claims

1. A transistor comprising:

a substrate comprising a Group III/V compound semiconductor material, the Group III/V compound semiconductor material having both a cubic crystalline phase structure and a hexagonal crystalline phase structure, the cubic crystalline phase structure positioned on the hexagonal crystalline phase structure, the hexagonal crystalline phase structure having a first region and a second region, the cubic crystalline phase structure being epitaxial to both the first region and the second region of the hexagonal crystalline phase structure;

a source region and a drain region, both the source region and the drain region positioned in the Group III/V compound semiconductor material;

a channel region in the Group III/V compound semiconductor material;

a gate over the channel region;

an optional backside contact; and

a source contact and electrode and a drain contact and electrode, the source contact and electrode positioned to provide electrical contact to the source region and the drain contact and electrode positioned to provide electrical contact to the drain region.

2. The transistor of claim 1, wherein:

the source region is in the first region of the hexagonal crystalline phase layer structure and the drain region is in the second region of the hexagonal crystalline phase layer structure;

the channel region is in the cubic crystalline phase region; and

the gate comprises a gate dielectric positioned over the channel region and a gate electrode positioned over the gate dielectric,

wherein the cubic crystalline phase structure has a length dimension, a width dimension and a height dimension, the width dimension corresponding to a gate length of the transistor, a portion of the cubic crystalline phase structure being tapered so that the gate length of the transistor is dependent on the height dimension.

3. The transistor of claim 2, wherein the Group III/V compound semiconductor material is a Group III-nitride.

4. The transistor of claim 2, wherein the channel region comprises a heterojunction at an interface between the hexagonal crystalline phase structure and the cubic crystalline phase structure, the transistor being a HEMT (“

high-electron-mobility transistor”

).

5. The transistor of claim 2, wherein the channel region comprises a heterojunction in the cubic crystalline phase structure and the transistor is a HEMT.

6. A device comprising a plurality of transistors of claim 2, wherein a first one of the transistors has a cubic crystalline phase structure with a first height, and a second one of the transistors has a cubic crystalline phase structure with a second height that is less than the first height, the gate length of the second transistor being greater than the gate length of the first transistor.

9. The transistor of claim 3, wherein the Group III-nitride is gallium nitride.

7. A MOSFET transistor comprising:

a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase formed in a groove, the groove comprising sidewalls having exposed {111} faces of a crystalline semiconductor, the Group III/V compound semiconductor material being a Group III-nitride, the Group III/V compound semiconductor material comprising an epitaxial hexagonal crystalline phase structure in the groove, the cubic crystalline phase structure being epitaxial to the hexagonal crystalline phase structure;

a source region and a drain region in the cubic crystalline phase;

a gate dielectric on the cubic crystalline phase between the source region and the drain region; and

a gate electrode on the gate dielectric.

8. The transistor of claim 7, wherein the Group III-nitride is gallium nitride.