Vertical bi-directional switches and method for making same

• US 10,644,146 B1
• Filed: 11/13/2018
• Issued: 05/05/2020
• Est. Priority Date: 11/13/2018
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Zitouni, Moaniss, Khemka, Vishnu, Qin, Ganming, Saxena, Tanuj, Gupta, Raghuveer Vankayala, Gibson, Mark Edward
• Primary Examiner(s): Sayadian, Hrayr A
• Application Number:
  US16/189,843
• Publication Number:
  US 20200152786A1
• Time in Patent Office: 539 Days
• Field of Search: None
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A vertical bi-directional device includes first and second conductive gates in a semiconductor layer with a first vertical gate oxide on a sidewall of the first conductive gate and a second vertical gate oxide on a sidewall of the second conductive gate. A first heavily doped region of a first conductivity type is at the surface adjacent the first conductive gate, and a second heavily doped region of the first conductive type is at the surface adjacent to the second conductive gate. Doped regions of the first conductivity type extend below the conductive gates towards a substrate. A doped region of a second conductivity type extends laterally from the first vertical gate oxide to the second vertical gate oxide, and a heavily doped region of the second conductivity type is at the surface of the semiconductor layer, between the first and second heavily doped regions of the first conductivity type.

Claims

1. A vertical bi-directional device comprising:

a substrate;

a semiconductor layer over the substrate;

a first conductive gate in the semiconductor layer, recessed from a top surface of the semiconductor layer;

a first gate oxide on a first sidewall and a bottom surface of the first conductive gate, wherein the first sidewall of the first conductive gate is perpendicular to a major surface of the substrate;

a second conductive gate in the semiconductor layer, recessed from the top surface of the semiconductor layer;

a second gate oxide on a first sidewall and a bottom surface of the second conductive gate, wherein the first sidewall of the second conductive gate is perpendicular to the major surface of the substrate;

a first insulator over a top surface of the first conductive gate, wherein the top surface of the first conductive gate is opposite the bottom surface of the first conductive gate;

a second insulator on a top surface of the second conductive gate, wherein the top surface of the second conductive gate is opposite the bottom surface of the second conductive gate

a first heavily doped region of a first conductivity type at a surface of the semiconductor layer, adjacent the first insulator;

a second heavily doped region of the first conductivity type at the surface of the semiconductor layer, adjacent the second insulator;

a first doped region of the first conductivity type under the first conductive gate, extending from the first gate oxide on the bottom surface of the first conductive gate towards the substrate;

a second doped region of the first conductivity type under the second conductive gate, extending from the second gate oxide on the bottom surface of the second conductive gate towards the substrate;

a first doped region of a second conductivity type, opposite the first conductivity type, under the top surfaces of the first and second conductive gates and extending laterally from the first gate oxide on the first sidewall of the first conductive gate to the second gate oxide on the first sidewall of the second conductive gate; and

a heavily doped region of the second conductivity type at the surface of the semiconductor layer, wherein the heavily doped region of the second conductivity type is laterally between the first and second heavily doped regions of the first conductivity type at the surface of the semiconductor layer.

2. The device of claim 1, further comprising:

a first shallow trench isolation (STI) region in the semiconductor layer above the first doped region of the second conductivity type; and

a second STI region in the semiconductor layer above the first doped region of the second conductivity type, wherein the first STI is between the first heavily doped region of the first conductivity type and the heavily doped region of the second conductivity type, and the second STI is between the heavily doped region of the second conductivity type and the second heavily doped region of the first conductivity type.

3. The device of claim 1, wherein a first vertical channel region is located between the first heavily doped region of the first conductivity type and the first doped region of the first conductivity type, adjacent the first sidewall of the first conductive gate, and a second vertical channel region is located between the second heavily doped region of the first conductivity type and the second doped region of the first conductivity type, adjacent the first sidewall of the second conductive gate.

4. The device of claim 1, further comprising:

a second doped region of the second conductivity type in the semiconductor layer between the heavily doped region of the second conductivity type and the first doped region of the second conductivity type.

5. The device of claim 1, wherein the semiconductor layer comprises:

a first epitaxial layer of the first conductivity type on the substrate;

a first epitaxial layer of the second conductivity type over the first epitaxial layer of the first conductivity type; and

a second epitaxial layer of the first conductive type over the first epitaxial layer of the second conductivity type, wherein a top surface of the second epitaxial layer of the first conductive type provides the top surface of the semiconductor layer, and wherein the first doped region of the first conductivity type under the first conductive gate extends from the first gate oxide through the first epitaxial layer of the second conductivity type, and the second doped region of the first conductivity type under the second conductive gate extends through the first epitaxial layer of the second conductivity type.

6. The device of claim 1, wherein the semiconductor layer comprises:

a first epitaxial layer of the first conductivity type on the substrate;

a second epitaxial layer of the second conductivity type over the first epitaxial layer of the first conductivity type, wherein a top surface of the second epitaxial layer of the second conductivity type provides the top surface of the semiconductor layer;

and the device further comprises;

a well region of the second conductivity type in the first epitaxial layer, wherein the first doped region of the first conductivity type under the first conductive gate extends vertically from the first gate oxide through the well region, and the second doped region of the first conductivity type under the second conductive gate extends vertically through the well region, and wherein the first and second conductive gates extend vertically through the second epitaxial layer and into the well region.

7. A method of forming a vertical bi-directional device, comprising:

forming a semiconductor layer over a substrate;

forming a shallow trench isolation (STI) region in the semiconductor layer;

forming a trench in the semiconductor layer, laterally spaced from the STI region;

forming a gate oxide layer along a bottom of the trench and along a sidewall of the trench;

performing a first implant through the bottom of the trench into the semiconductor layer to form a first doped region of a first conductivity type extending from the gate oxide along the bottom of the trench towards the substrate;

forming a conductive gate in the trench, wherein a top surface of the conductive gate is recessed as compared to a top surface of the semiconductor layer;

forming an insulator over the conductive gate, wherein a top surface of the insulator is coplanar with the top surface of the semiconductor layer;

performing a second implant through a top surface of the semiconductor layer to form a first doped region of a second conductivity type, opposite the first conductivity type, wherein the first doped region extends laterally from the gate oxide layer along the sidewall of the trench and under the STI region;

performing a third implant through the top surface of the semiconductor layer to form a first heavily doped region of the first conductivity type laterally between the insulator and the STI region; and

performing a fourth implant through the top surface of the semiconductor layer to form a first heavily doped region of the second conductivity at the top surface of the semiconductor layer adjacent the STI region, wherein the STI region is laterally between the first heavily doped region of the first conductivity type and the first heavily doped region of the second conductivity type.

8. The method of claim 7, wherein forming the semiconductor layer over the substrate comprises:

epitaxially growing a first epitaxial layer of the first conductivity type; and

epitaxially growing a second epitaxial layer of the first conductivity type on the first epitaxial layer of the first conductivity type, wherein a top surface of the second epitaxial layer of the first conductivity type provides the top surface of the semiconductor layer.

9. The method of claim 8, further comprising:

performing a fifth implant through the top surface of the semiconductor layer to form a well region of the second conductivity type which extends towards the substrate, wherein the second implant is performed into the well region.

10. The method of claim 9, wherein the well region of the second conductivity type does not extend all the way to the substrate, and the first doped region of the first conductivity type extends from the gate oxide layer along the bottom of the trench towards the substrate fully through the well region.

11. The method of claim 9, further comprising:

performing a sixth implant through the top surface of the semiconductor layer to form a second doped region of the second conductivity type, wherein the semiconductor layer between the STI region and the insulator is masked during the sixth implant.

12. The method of claim 11, wherein a portion of the second epitaxial layer of the first conductivity type remains as the first conductivity type laterally between the STI and the insulator and vertically between the first heavily doped region of the first conductivity type and the first doped region of the second conductivity type, and extending under the STI region.

13. The method of claim 11, wherein the heavily doped region of the second conductivity type is formed in the second doped region of the second conductivity type.

14. The method of claim 7, wherein forming the semiconductor layer over the substrate comprises:

epitaxially growing a first epitaxial layer of the first conductivity type on the substrate;

epitaxially growing a first epitaxial layer of the second conductivity type on the first epitaxial layer of the first conductivity type; and

epitaxially growing a second epitaxial layer of the first conductivity type on the second epitaxial layer, wherein a top surface of the third epitaxial layer provides the top surface of the semiconductor layer.

15. The method of claim 14, wherein performing the first implant is performed such that the first doped region of a first conductivity type extends from the gate oxide along the bottom of the trench through the first epitaxial layer of the first conductivity type.

16. The method of claim 15, further comprising:

performing a fifth implant through the top surface of the second epitaxial layer of the first conductivity type to form a second doped region of the second conductivity type, wherein the second doped region of the second conductivity type contacts the first doped region of the second conductivity type.

17. The method of claim 16, wherein the heavily doped region of the second conductivity type is formed in the second doped region of the second conductivity type.

18. The method of claim 17, wherein the first heavily doped region of the first conductivity type is formed in the second epitaxial layer of the first conductivity type.

19. A vertical bi-directional device comprising:

a substrate having a first conductivity type;

a first semiconductor layer having the first conductivity type on the substrate;

a second semiconductor layer having the first conductivity type and on the first semiconductor layer;

a first shallow trench isolation (STI) region and a second STI region in the second semiconductor layer;

a well region in the first semiconductor layer having a second conductivity type, opposite the first conductivity type;

a first conductive gate in the second semiconductor layer and extending into the well region of the first semiconductor layer, recessed from a top surface of the second semiconductor layer;

a first gate oxide on a first sidewall and a bottom surface of the first conductive gate, wherein the first sidewall of the first conductive gate is perpendicular to a major surface of the substrate;

a second conductive gate in the second semiconductor layer and extending into the well region of the first semiconductor layer, recessed from a top surface of the second semiconductor layer;

a second gate oxide on a first sidewall and a bottom surface of the second conductive gate, wherein the first sidewall of the second conductive gate is perpendicular to a major surface of the substrate, wherein the first and second STI regions are laterally between the first and second conductive gates;

a first insulator over a top surface of the first conductive gate, wherein the top surface of the first conductive gate is opposite the bottom surface of the first conductive gate;

a second insulator on a top surface of the second conductive gate, wherein the top surface of the second conductive gate is opposite the bottom surface of the second conductive gate a first heavily doped region of the first conductivity type at the top surface of the second semiconductor layer, laterally between the first insulator and the first STI;

a second heavily doped region of the first conductivity type at the top surface of the second semiconductor layer, laterally between the second STI and the second insulator;

a first doped region of the first conductivity type under the first conductive gate, extending from the first gate oxide on the bottom surface of the first conductive gate to a bottom of the well region;

a second doped region of the first conductivity type under the second conductive gate, extending from the second gate oxide on the bottom surface of the second conductive gate to the bottom of the well region;

a first doped region of a second conductivity type in the well region, under the first and second STI regions, and extending laterally from the first gate oxide on the first sidewall of the first conductive gate to the second gate oxide on the first sidewall of the second conductive gate; and

a heavily doped region of the second conductivity type at the top surface of the second semiconductor layer, laterally between the first and second STI regions.

20. The device of claim 19, further comprising:

a second doped region of the second conductivity type in the second semiconductor layer vertically between the heavily doped region of the second conductivity type and the first doped region of the second conductivity type, wherein the second dope region physically contacts both the heavily doped region of the second conductivity type and the first doped region of the second conductivity type.