Tunnel field-effect transistor with reduced subthreshold swing

• US 10,644,150 B2
• Filed: 06/04/2018
• Issued: 05/05/2020
• Est. Priority Date: 06/04/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Miao, Xin, Zhang, Chen, Cheng, Kangguo, Xu, Wenyu
• Primary Examiner(s): Liu, Benjamin T
• Application Number:
  US15/996,638
• Publication Number:
  US 20190371911A1
• Time in Patent Office: 701 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/30621 Vapour phase etching
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/66356 Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a source layer on a semiconductor substrate;

forming a channel layer on the source layer;

forming a drain layer on the channel layer;

patterning the source, channel and drain layers into at least one fin;

forming a cap layer on a lower portion of the at least one fin comprising the source layer and part of the channel layer;

forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer;

wherein the cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer; and

forming a spacer layer on an upper portion of the at least one fin comprising the drain layer and another part of the channel layer;

wherein forming the cap layer comprises epitaxially growing the cap layer on the lower portion of the at least one fin; and

wherein the spacer layer prevents epitaxial growth of the cap layer from the upper portion of the at least one fin.

2. The method according to claim 1, wherein the cap layer comprises a III-V compound semiconductor material.

3. The method according to claim 2, wherein the source, channel and drain layers each comprise a III-V compound semiconductor material different from the III-V compound semiconductor material of the cap layer.

4. The method according to claim 1, wherein the cap layer has larger band gap than a band gap of the source and channel layers.

5. The method according to claim 1, further comprising doping the source and drain layers to have opposite doping types from each other.

6. The method according to claim 1, wherein the at least one fin extends perpendicularly with respect to a top surface of the semiconductor substrate.

7. The method according to claim 1, wherein a thickness of the cap layer is in the range of about 1 nm to about 10 nm.

8. The method according to claim 1, wherein the cap layer covers a tunnel junction between the source layer and the channel layer.