Buried-channel low noise transistors and methods of making such devices
First Claim
1. An integrated circuit product, comprising:
- a base semiconductor substrate;
a buried insulation layer positioned above said base semiconductor layer;
an active region positioned above said buried insulation layer;
at least one active transistor positioned in said active region, said at least one active transistor comprising;
a gate that comprises a gate structure;
first and second source/drain regions positioned on opposite sides of said gate, said first and second source/drain regions comprising doped epitaxial semiconductor material that is doped with a dopant material of a first type;
a gate length that extends in a gate length direction; and
a contact-poly-pitch (CPP) dimension that extends in said gate length direction; and
a doped region positioned below said gate, said doped region having a lateral width in said gate length direction that is at least substantially equal to said CPP dimension, said doped region being doped with a dopant material of said first type, wherein a first portion of said doped region is positioned vertically above an interface between said active region and said buried insulation layer and a second portion of said doped region is positioned vertically below said interface.
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Accused Products
Abstract
One illustrative integrated circuit product disclosed herein includes at least one transistor formed on an active region of on an SOI substrate, the transistor comprising a gate that includes a gate structure, first and second source/drain regions positioned on opposite sides of the gate, the first and second source/drain regions comprising doped epitaxial semiconductor material that is doped with a dopant material of a first type, and a doped region positioned below the gate, wherein the doped region has a lateral width that is at least substantially equal to the CPP (contact-poly-pitch) dimension of the transistor and is doped with a dopant material of the first type, wherein a first portion of the doped region is positioned vertically above an interface between the active region and a buried insulation layer of the SOI substrate and a second portion of the doped region is positioned vertically below the interface.
7 Citations
20 Claims
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1. An integrated circuit product, comprising:
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a base semiconductor substrate; a buried insulation layer positioned above said base semiconductor layer; an active region positioned above said buried insulation layer; at least one active transistor positioned in said active region, said at least one active transistor comprising; a gate that comprises a gate structure; first and second source/drain regions positioned on opposite sides of said gate, said first and second source/drain regions comprising doped epitaxial semiconductor material that is doped with a dopant material of a first type; a gate length that extends in a gate length direction; and a contact-poly-pitch (CPP) dimension that extends in said gate length direction; and a doped region positioned below said gate, said doped region having a lateral width in said gate length direction that is at least substantially equal to said CPP dimension, said doped region being doped with a dopant material of said first type, wherein a first portion of said doped region is positioned vertically above an interface between said active region and said buried insulation layer and a second portion of said doped region is positioned vertically below said interface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. An integrated circuit product, comprising:
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a base semiconductor substrate; a buried insulation layer positioned above said base semiconductor layer; an active region positioned above said buried insulation layer; a transistor positioned in said active region, said transistor comprising; a gate that comprises a gate structure; first and second source/drain regions positioned on opposite sides of said gate, said first and second source/drain regions comprising doped epitaxial semiconductor material that is doped with a dopant material of a first type; a gate length that extends in a gate length direction, wherein said active region has a lateral width in said gate length direction; and a contact-poly-pitch (CPP) dimension that extends in said gate length direction; and a doped region positioned below said gate, said doped region having a lateral width in said gate length direction that is at least substantially equal to said CPP dimension but less than said lateral width of said active region, said doped region being doped with a dopant material of said first type, wherein a first portion of said doped region is positioned vertically above an interface between said active region and said buried insulation layer and a second portion of said doped region is positioned vertically below said interface, wherein a lateral midpoint of said doped region is in substantial vertical alignment with a lateral midpoint of said gate of said transistor. - View Dependent Claims (19, 20)
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Specification