Semiconductor device and manufacturing method thereof

• US 10,644,154 B2
• Filed: 10/29/2018
• Issued: 05/05/2020
• Est. Priority Date: 04/15/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Tsai, Ching-Wei, Wang, Chih-Hao, Lien, Wai-Yi
• Primary Examiner(s): Gumedzoe, Peniel M
• Assistant Examiner(s): Johnson, Christopher A
• Application Number:
  US16/174,196
• Publication Number:
  US 20190067482A1
• Time in Patent Office: 554 Days
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02524 Group 14 semiconducting materials
• CPC Class Codes: H01L 21/02529 Silicon carbide
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02645 Seed materials
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for manufacturing a semiconductor device includes forming a fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. An isolation insulating layer is formed so that the channel layer of the fin structure protrudes from the isolation insulating layer and a part of or an entirety of the oxide layer is embedded in the isolation insulating layer. A gate structure is formed over the fin structure. A recessed portion is formed by etching a part of the fin structure not covered by the gate structure such that the oxide layer is exposed. A recess is formed in the exposed oxide layer. An epitaxial seed layer in the recess in the oxide layer. An epitaxial layer is formed in and above the recessed portion. The epitaxial layer is in contact with the epitaxial seed layer.

Claims

1. A Fin Field-Effect Transistor (Fin FET) device, comprising:

a fin structure including a well layer, an oxide layer, and a channel layer sequentially stacked on each other;

a gate stack including a gate electrode layer covering a portion of the fin structure;

first and second seed layers formed on side surfaces of the oxide layer;

a source disposed on a first side of the channel layer, and protruding from the well layer and the first and second seed layers; and

a drain disposed on a second side of the channel layer opposing the first side, and protruding from the well layer and the first and second seed layers,

wherein the source and the drain contact the oxide layer.

2. The Fin FET device of claim 1, wherein the oxide layer includes SiGe oxide.

3. The Fin FET device of claim 1, wherein the first and second seed layers include amorphous silicon.

4. The Fin FET device of claim 1, wherein:

the Fin FET device is an n-type Fin FET, and

the source and the drain include at least one of SiC, SiCP and SiP.

5. The Fin FET device of claim 1, wherein:

the Fin FET device is a p-type Fin FET, and

the source and the drain include at least one of SiGe and Ge.

6. The Fin FET device of claim 1, wherein the source and the drain include first bottom portions filling the recessed portions of the fin structure, and second upper portions having a width first increasing and then decreasing in a direction from the well layer to the channel layer.

7. The Fin FET device of claim 1, wherein a width of the first and second seed layers is 1 nm to 10 nm.

8. The Fin FET device of claim 1, wherein:

the first and second seed layers are disposed at a level above interfaces between the source and the well layer and between the drain and the well layer.

9. A Fin Field-Effect Transistor (Fin FET) device;

comprising;

an isolation insulating layer;

a fin structure including a well layer, an oxide layer, and a channel layer sequentially stacked on each other;

first and second seed layers disposed at least on side surfaces of the well layer to separate the side surfaces of the well layer from the isolation insulating layer;

a gate stack including a gate electrode layer covering a portion of the fin structure;

a source disposed on a first side of the channel layer, and protruding from the well layer and the first and second seed layers; and

a drain disposed on a second side of the channel layer opposing the first side, and protruding from the well layer and the first and second seed layers.

10. The Fin FET device of claim 9, wherein the oxide layer includes SiGe oxide.

11. The Fin FET device of claim 9, wherein the first and second seed layers include amorphous silicon.

12. The Fin FET device of claim 9, wherein:

the Fin FET device is an n-type Fin FET, and

the source and the drain include at least one of SiC, SiCP and SiP.

13. The Fin FET device of claim 9, wherein:

the Fin FET device is a p-type Fin FET, and

the source and the drain include at least one of SiGe and Ge.

14. The Fin FET device of claim 9, wherein the source and the drain include first bottom portions filling the recessed portions of the fin structure, and second upper portions having a width first increasing and then decreasing in a direction from the well layer to the channel layer.

15. The Fin FET device of claim 9, wherein a width of the first and second seed layers is 1 nm to 10 nm.

16. A Fin Field-Effect Transistor (Fin FET) device, comprising:

a fin structure including a well layer, an oxide layer, and a channel layer sequentially stacked on each other;

first and second seed layers disposed on side surfaces of the well layer and side surfaces of the oxide layer;

a first dielectric layer disposed between the first seed layer and the well layer and a second dielectric layer disposed between the second seed layer and the well layer;

a gate stack including a gate electrode layer covering a portion of the fin structure;

a source disposed on a first side of the channel layer, and protruding from the well layer and the first and second seed layers; and

a drain disposed on a second side of the channel layer opposing the first side, and protruding from the well layer and the first and second seed layers.

17. The Fin FET device of claim 16, wherein the oxide layer includes SiGe oxide.

18. The Fin FET device of claim 16, wherein the first and second seed layers include amorphous silicon.

19. The Fin FET device of claim 16, wherein:

the Fin FET device is an n-type Fin FET, and

the source and the drain include at least one of SiC, SiCP and SiP.

20. The Fin FET device of claim 16, wherein:

the Fin FET device is a p-type Fin FET, and

the source and the drain include at least one of SiGe and Ge.