Method for manufacturing a semiconductor device with horizontally aligned semiconductor channels

• US 10,644,155 B2
• Filed: 04/18/2018
• Issued: 05/05/2020
• Est. Priority Date: 05/30/2017
• Status: Active Grant

• Current Assignee: Korea Advanced Institute of Science and Technology
• Original Assignee: Korea Advanced Institute of Science and Technology
• Inventors: Kim, Hyung-jun, Kim, Sanghyeon, Shim, Jae-Phil
• Primary Examiner(s): Green, Telly D
• Application Number:
  US15/955,690
• Publication Number:
  US 20180350988A1
• Time in Patent Office: 748 Days
• Field of Search: None
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7849 the means being provided under the channel

Abstract

Disclosed is a semiconductor device, which includes: forming a first channel layer including a Group III-V compound or germanium (Ge) and having a first semiconductor characteristics on a first substrate; forming a second channel layer including a Group III-V compound or germanium (Ge) and having a second semiconductor characteristics different from the first semiconductor characteristics on the first channel layer; forming a bonding layer containing an oxide on a second channel layer; allowing the bonding layer to be bound to the second substrate so that a structure including the bonding layer, the second channel layer, the first channel layer and the first substrate may be stacked on the second substrate; removing the first substrate stacked on the second substrate; and removing the first channel layer from a partial region of the structure stacked on the second substrate.

Claims

1. A method for manufacturing a semiconductor device, which comprises:

forming a first channel layer comprising a Group III-V compound or germanium (Ge) and having a first semiconductor characteristics on a first substrate;

forming a second channel layer comprising a Group III-V compound or germanium (Ge) and having a second semiconductor characteristics different from the first semiconductor characteristics on the first channel layer by an epitaxial growth process;

forming a bonding layer containing an oxide on the second channel layer opposite to the first channel layer;

stacking a structure comprising the bonding layer, the second channel layer, the first channel layer and the first substrate on a second substrate by allowing the bonding layer to be bound to the second substrate, wherein said forming the first channel layer and said forming the second channel layer are carried out repeatedly, so that the structure has a structure in which the first channel and the second channel layer are stacked alternately many times;

removing the first substrate stacked on the second substrate;

removing the first channel layer from a first region of the structure stacked on the second substrate by selective etching, and

removing the second channel layer from a second region of the structure stacked on the second substrate by selective etching, wherein the second region is a different region from the first region in a plan view,

wherein the selective etching is not performed in a first adjacent region of the structure which is adjacent to the first region and a second adjacent region of the structure which is adjacent to the second region, and the first adjacent region and the second adjacent region support the second channel layer in the first region and the first channel layer in the second region, respectively, so that the second channel layer in the first region and the first channel layer in the second region have a nanoplate or nanowire shape in space,

wherein said forming the bonding layer on the second channel layer and said stacking the structure on the second substrate are performed after said forming the second channel layer on the first channel layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein said forming the first channel layer comprises forming a sacrificial layer on the first substrate,

the first channel layer is positioned on the sacrificial layer, and

said removing the first substrate comprises removing the sacrificial layer by etching.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the sacrificial layer comprises aluminum arsenic (AlAs) or indium aluminum arsenic (InAlAs).

4. The method for manufacturing a semiconductor device according to claim 1, which further comprises forming a barrier layer on the first channel layer, before said forming the second channel layer.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the barrier layer has a lattice constant different from the lattice constant of at least one of the first channel layer and the second channel layer.

6. The method for manufacturing a semiconductor device according to claim 4, wherein the barrier layer comprises aluminum gallium arsenic (AlGaAs) or indium aluminum arsenic (InAlAs).

7. The method for manufacturing a semiconductor device according to claim 1, which further comprises forming an additional bonding layer on the second substrate, before said stacking onto the second substrate.

8. The method for manufacturing a semiconductor device according to claim 1, which further comprises removing the first channel layer and the second channel layer from a third region disposed between the first region and the second region in the plan view so that the first region and the second region are spaced apart from each other, wherein the third region is a different region from the first adjacent region and the second adjacent region.

9. The method for manufacturing a semiconductor device according to claim 1, wherein the first channel layer comprises gallium arsenic (GaAs) or indium gallium arsenic (InGaAs), and the second channel layer comprises germanium (Ge) or gallium arsenic (GaAs).