Thin film transistor and fabricating method thereof, array substrate and display device

• US 10,644,160 B2
• Filed: 01/29/2018
• Issued: 05/05/2020
• Est. Priority Date: 05/11/2017
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Chen, Jiangbo, Song, Young Suk, Sun, Hongda, Wang, Guoying, Liu, Wei
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US16/077,846
• Publication Number:
  US 20200035834A1
• Time in Patent Office: 827 Days
• CPC Class Codes: H01L 21/44 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The present disclosure relates to a thin film transistor, a method for fabricating the same, an array substrate, a method for fabricating the same, and a display device. The thin film transistor includes an active layer disposed on a base substrate and a gate stack disposed on the active layer. The gate stack includes: a gate insulating layer disposed on the active layer; a gate electrode disposed on the gate insulating layer; a capping layer disposed on the gate electrode, wherein the capping layer capturing oxygen atoms more easily than the gate electrode.

Claims

1. A thin film transistor comprising an active layer disposed on a base substrate and a gate stack disposed on the active layer, wherein the gate stack comprises:

a gate insulating layer disposed on the active layer;

a gate electrode disposed on the gate insulating layer;

a capping layer disposed on the gate electrode and being more easily to trap oxygen atoms than the gate electrode, wherein the capping layer comprises a gallium-containing oxide, and wherein the gallium-containing oxide is oxygen deficient.

2. The thin film transistor according to claim 1, wherein the gallium-containing oxide comprises at least one of the following materials:

IGZO, GZO, IGO, gallium oxide, or a combination thereof.

3. The thin film transistor according to claim 1, wherein a material of the capping layer and a material of the active layer are the same.

4. The thin film transistor according to claim 1, wherein the thin film transistor further comprises a dielectric layer disposed on the capping layer, wherein the dielectric layer covers an upper surface of the active layer.

5. The thin film transistor according to claim 4, wherein the thin film transistor further comprises a first contact portion disposed on the dielectric layer and a first hole in the dielectric layer, wherein the first contact portion is connected to the source/drain region of the thin film transistor via the first hole.

6. An array substrate comprising the thin film transistor according to claim 1.

7. The array substrate according to claim 6, wherein the array substrate further comprises:

a first wiring in a dielectric layer, the first wiring having the same structure as the gate stack, a top surface of the first wiring being higher than a top surface of the active layer;

a second contact portion on the dielectric layer;

a second hole in the dielectric layer,

wherein the second contact portion is connected to the first wiring via the second hole.

8. The array substrate according to claim 7, wherein the array substrate further comprises:

a light shielding layer disposed between the active layer and the base substrate to block light from below the active layer from entering the active layer;

a second wiring being in the same layer as the light shielding layer;

a third contact portion on the dielectric layer;

a third hole passing through the dielectric layer and extending into the base substrate,

wherein the third contact portion is connected to the second wiring through the third hole.

9. The array substrate according to claim 8, wherein the array substrate further comprises:

a buffer layer disposed between the active layer and the base substrate, wherein the buffer layer covers an upper surface of the light shielding layer, an upper surface of the second wiring and an upper surface of the base substrate;

a passivation layer on a first contact portion, the second contact portion and the third contact portion.

10. A display device comprising the array substrate according to claim 8.

11. A display device comprising the array substrate according to claim 9.

12. A display device comprising the array substrate according to claim 7.

13. A display device comprising the array substrate according to claim 6.

14. A method for fabricating a thin film transistor, comprising:

forming an active layer on a base substrate;

forming a gate stack on the active layer,

wherein, the gate stack comprises;

a gate insulating layer on the active layer;

a gate electrode on the gate insulating layer;

a capping layer on the gate electrode, the capping layer being more easily to trap oxygen atoms than the gate electrode, wherein the capping layer comprises a gallium-containing oxide, and wherein the gallium-containing oxide is oxygen deficient.

15. The method for fabricating a thin film transistor according to claim 14, wherein the gallium-containing oxide comprises at least one of the following materials:

IGZO, GZO, IGO, gallium oxide, or a combination thereof, and forming the gate stack comprises;

forming an insulating material layer on the active layer;

forming a conductive layer on the insulating material layer;

forming a capping material layer on the conductive layer;

performing a patterning to form the gate stack.

16. A method for fabricating an array substrate, comprising the method for fabricating a thin film transistor according to claim 14.

17. The method for fabricating an array substrate according to claim 16, further comprising:

before forming the active layer, forming a light shielding layer and a second wiring on the base substrate, wherein the second wiring and the light shielding layer are simultaneously formed, and wherein the light shielding layer is capable to block the light from below the active layer from entering the active layer;

after forming the active layer, forming a first wiring on the base substrate, wherein the first wiring and the gate stack are formed simultaneously, and wherein the first wiring has the same structure as the gate stack;

after forming the gate stack and before forming dielectric layer, performing a plasma treatment on an upper surface of the capping layer and an upper surface of the active layer.