Methods and devices for forming thermoelectric elements

• US 10,644,216 B2
• Filed: 04/20/2018
• Issued: 05/05/2020
• Est. Priority Date: 03/25/2014
• Status: Active Grant

• Current Assignee: Matrix Industries, Inc.
• Original Assignee: Matrix Industries, Inc.
• Inventors: Boukai, Akram I., Tham, Douglas W., Liang, Haifan
• Primary Examiner(s): Jung, Michael
• Application Number:
  US15/958,231
• Publication Number:
  US 20180240957A1
• Time in Patent Office: 746 Days
• Field of Search: None
• CPC Class Codes: H10N 10/01 Manufacture or treatment
• CPC Class Codes: H10N 10/17 characterised by the structure or configuration of the cell or thermocouple forming the device
• CPC Class Codes: H10N 10/855 comprising compounds containing boron, carbon, oxygen or nitrogen

Abstract

The present disclosure provides a thermoelectric element comprising a flexible semiconductor substrate having exposed surfaces with a metal content that is less than about 1% as measured by x-ray photoelectron spectroscopy (XPS) and a figure of merit (ZT) that is at least about 0.25, wherein the flexible semiconductor substrate has a Young'"'"'s Modulus that is less than or equal to about 1×10⁶ pounds per square inch (psi) at 25° C.

Claims

1. A method for forming a thermoelectric element having a figure of merit (ZT) that is at least 0.25 at 25°

C., comprising;

(a) providing a reaction space comprising a semiconductor substrate in electrical communication with a plurality of electrodes, wherein said semiconductor substrate is substantially free of a metallic coating; and

(b) using said plurality of electrodes to direct electrical current through said semiconductor substrate at a current density of at least 0.1 mA/cm² and an electrical potential of at least 1 volt (V), to form a thermoelectric element comprising a pattern of holes, wherein said thermoelectric element has said ZT that is at least 0.25 at 25°

C.

2. The method of claim 1, wherein said plurality of electrodes comprises a working electrode and a counter electrode that are each in electrical communication with said semiconductor substrate.

3. The method of claim 1, further comprising providing an etching solution in said reaction space, wherein during (b), said etching solution is in contact with said semiconductor substrate.

4. The method of claim 3, wherein said etching solution comprises an acid.

5. The method of claim 1, wherein said pattern of holes comprises a disordered pattern of holes.

6. The method of claim 1, wherein said pattern of holes is polydisperse.

7. The method of claim 1, wherein said thermoelectric element has a metal content of less than 1% as measured by x-ray photoelectron spectroscopy (XPS).

8. The method of claim 7, wherein said metal content is less than or equal to 0.1% as measured by XPS.

9. The method of claim 8, wherein said metal content is less than or equal to 0.01% as measured by XPS.

10. The method of claim 9, wherein said metal content is less than or equal to 0.001% as measured by XPS.

11. The method of claim 1, wherein said ZT is at least 0.3 at 25°

C.

12. The method of claim 11, wherein said ZT is at least 0.6 at 25°

C.

13. The method of claim 12, wherein said ZT is at least 0.8 at 25°

C.

14. The method of claim 13, wherein said ZT is at least 1.0 at 25°

C.

15. The method of claim 14, wherein said ZT is at least 1.3 at 25°

C.

16. The method of claim 1, wherein said current density is at least 1 mA/cm².

17. The method of claim 16, wherein said current density is at least 10 mA/cm².

18. The method of claim 17, wherein said current density is less than or equal to 50 mA/cm².

19. The method of claim 1, wherein a hole of said pattern of holes has a surface roughness from 0.1 nanometers (nm) to 50 nm as measured by transmission electron microscopy (TEM).