Array substrate for OLED display device

• US 10,644,237 B2
• Filed: 01/13/2017
• Issued: 05/05/2020
• Est. Priority Date: 08/03/2016
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Shi, Longqiang
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US15/329,329
• Publication Number:
  US 20180337333A1
• Time in Patent Office: 1,208 Days
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 33/00 Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof H10K50/00 takes precedence; devices consisting of a plurality of semiconductor components formed in or on a common substrate and including semiconductor components having potential barriers, specially adapted for light emission H01L27/15; semiconductor lasers H01S5/00
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Disclosed are an array substrate of an OLED display device and a method for manufacturing the same. Thin-film transistors having different functions can have different electrical properties. The array substrate includes a base substrate, a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer which are arranged sequentially from bottom to top. A plurality of driving units are formed on the array substrate, and each of the driving units comprises a first thin-film transistor and a second thin-film transistor.

Claims

1. An array substrate of an OLED display device, comprising a base substrate, a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer which are arranged sequentially from bottom to top;

wherein a plurality of driving units are formed on the array substrate, and each of the driving units comprises a first thin-film transistor and a second thin-film transistor;

wherein an active channel layer of the first thin-film transistor and an active channel layer of the second thin-film transistor are arranged on the semiconductor layer;

wherein a gate of the first thin-film transistor, and a source and a drain of the second thin-film transistor are arranged in the first metal layer;

wherein a gate of the second thin-film transistor, and a source and a drain of the first thin-film transistor are arranged in the second metal layer; and

wherein the gate of the second thin-film transistor is connected to the drain of the first thin-film transistor.

2. The array substrate according to claim 1, wherein the gate of the second thin-film transistor and the drain of the first thin-film transistor are connected with each other to form an integrated structure.

3. The array substrate according to claim 2, wherein doping areas are formed at two ends of the active channel layer.

4. The array substrate according to claim 1, wherein the active channel layer of the first thin-film transistor and the active channel layer of the second thin-film transistor are made of indium gallium zinc oxide.

5. The array substrate according to claim 1, wherein in the second thin-film transistor, the source and the drain are connected to the active channel layer through via holes running through the first insulating layer.

6. The array substrate according to claim 1, wherein in the first thin-film transistor, the source and the drain are connected to the active channel layer through via holes running through the first insulating layer and the second insulating layer.

7. The array substrate according to claim 1, wherein a transparent electrode layer is further formed on the third insulating layer;

and

wherein a pixel electrode arranged on the transparent electrode layer is connected to the drain of the second thin-film transistor through a via hole running through the second insulating layer and the third insulating layer.

8. A method for manufacturing an array substrate of an OLED display device,

wherein the array substrate of the OLED display device comprises a base substrate, a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer which are arranged sequentially from bottom to top;

wherein a plurality of driving units are formed on the array substrate, and each of the driving units comprises a first thin-film transistor and a second thin-film transistor;

wherein an active channel layer of the first thin-film transistor and an active channel layer of the second thin-film transistor are arranged on the semiconductor layer;

wherein a gate of the first thin-film transistor, and a source and a drain of the second thin-film transistor are arranged in the first metal layer; and

wherein a gate of the second thin-film transistor, and a source and a drain of the first thin-film transistor are arranged in the second metal layer; and

wherein the gate of the second thin-film transistor is connected to the drain of the first thin-film transistor; and

wherein the method includes steps of;

forming a pattern of a semiconductor layer on a base substrate by a mask patterning procedure, wherein the pattern of the semiconductor layer includes patterns of an active channel layer of a first thin-film transistor and an active channel layer of a second thin-film transistor in each driving unit;

forming a pattern of a first insulating layer by a mask patterning procedure based on the pattern formed in a preceding step, wherein the pattern of the first insulating layer includes patterns of via holes in the second thin-film transistor;

forming doping areas in the active channel layer of the second thin-film transistor by a plasma doping procedure based on the pattern formed in a preceding step;

forming a pattern of a first metal layer by a mask patterning procedure based on the pattern formed in a preceding step;

wherein the pattern of the first metal layer includes patterns of a gate of the first thin-film transistor, and a source and a drain of the second thin-film transistor;

forming a pattern of a second insulating layer by a mask patterning procedure based on the pattern formed in a preceding step, wherein the pattern of the second insulating layer includes patterns of via holes in the first thin-film transistor;

forming doping areas in the active Channel layer of the first thin-film transistor by a plasma doping procedure based on the pattern formed in a preceding step;

forming a pattern of a second metal layer by a mask patterning procedure based on the pattern formed in a preceding step, wherein the pattern of the second metal layer includes patterns of a gate of the second thin-film transistor, and a source and a drain of the first thin-film transistor; and

forming a pattern of a third insulating layer by a mask patterning procedure based on the pattern formed in a preceding step, wherein the pattern of the third insulating layer includes a pattern of a via hole of a pixel electrode.

9. The method according to claim 8, further including a step of:

forming a pattern of a transparent electrode layer by a mask patterning procedure based on the pattern formed in a preceding step, wherein the pattern of the transparent electrode layer includes a pattern of a pixel electrode connected to the drain of the second thin-film transistor.

10. The method according to claim 8, wherein the active channel layer of the first thin-film transistor and the active channel layer of the second thin-film transistor are made of indium gallium zinc oxide.