Array substrate for OLED display device
First Claim
1. An array substrate of an OLED display device, comprising a base substrate, a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer which are arranged sequentially from bottom to top;
- wherein a plurality of driving units are formed on the array substrate, and each of the driving units comprises a first thin-film transistor and a second thin-film transistor;
wherein an active channel layer of the first thin-film transistor and an active channel layer of the second thin-film transistor are arranged on the semiconductor layer;
wherein a gate of the first thin-film transistor, and a source and a drain of the second thin-film transistor are arranged in the first metal layer;
wherein a gate of the second thin-film transistor, and a source and a drain of the first thin-film transistor are arranged in the second metal layer; and
wherein the gate of the second thin-film transistor is connected to the drain of the first thin-film transistor.
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Accused Products
Abstract
Disclosed are an array substrate of an OLED display device and a method for manufacturing the same. Thin-film transistors having different functions can have different electrical properties. The array substrate includes a base substrate, a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer which are arranged sequentially from bottom to top. A plurality of driving units are formed on the array substrate, and each of the driving units comprises a first thin-film transistor and a second thin-film transistor.
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Citations
10 Claims
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1. An array substrate of an OLED display device, comprising a base substrate, a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer which are arranged sequentially from bottom to top;
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wherein a plurality of driving units are formed on the array substrate, and each of the driving units comprises a first thin-film transistor and a second thin-film transistor; wherein an active channel layer of the first thin-film transistor and an active channel layer of the second thin-film transistor are arranged on the semiconductor layer; wherein a gate of the first thin-film transistor, and a source and a drain of the second thin-film transistor are arranged in the first metal layer; wherein a gate of the second thin-film transistor, and a source and a drain of the first thin-film transistor are arranged in the second metal layer; and wherein the gate of the second thin-film transistor is connected to the drain of the first thin-film transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for manufacturing an array substrate of an OLED display device,
wherein the array substrate of the OLED display device comprises a base substrate, a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer which are arranged sequentially from bottom to top; -
wherein a plurality of driving units are formed on the array substrate, and each of the driving units comprises a first thin-film transistor and a second thin-film transistor; wherein an active channel layer of the first thin-film transistor and an active channel layer of the second thin-film transistor are arranged on the semiconductor layer; wherein a gate of the first thin-film transistor, and a source and a drain of the second thin-film transistor are arranged in the first metal layer; and wherein a gate of the second thin-film transistor, and a source and a drain of the first thin-film transistor are arranged in the second metal layer; and wherein the gate of the second thin-film transistor is connected to the drain of the first thin-film transistor; and wherein the method includes steps of; forming a pattern of a semiconductor layer on a base substrate by a mask patterning procedure, wherein the pattern of the semiconductor layer includes patterns of an active channel layer of a first thin-film transistor and an active channel layer of a second thin-film transistor in each driving unit; forming a pattern of a first insulating layer by a mask patterning procedure based on the pattern formed in a preceding step, wherein the pattern of the first insulating layer includes patterns of via holes in the second thin-film transistor; forming doping areas in the active channel layer of the second thin-film transistor by a plasma doping procedure based on the pattern formed in a preceding step; forming a pattern of a first metal layer by a mask patterning procedure based on the pattern formed in a preceding step;
wherein the pattern of the first metal layer includes patterns of a gate of the first thin-film transistor, and a source and a drain of the second thin-film transistor;forming a pattern of a second insulating layer by a mask patterning procedure based on the pattern formed in a preceding step, wherein the pattern of the second insulating layer includes patterns of via holes in the first thin-film transistor; forming doping areas in the active Channel layer of the first thin-film transistor by a plasma doping procedure based on the pattern formed in a preceding step; forming a pattern of a second metal layer by a mask patterning procedure based on the pattern formed in a preceding step, wherein the pattern of the second metal layer includes patterns of a gate of the second thin-film transistor, and a source and a drain of the first thin-film transistor; and forming a pattern of a third insulating layer by a mask patterning procedure based on the pattern formed in a preceding step, wherein the pattern of the third insulating layer includes a pattern of a via hole of a pixel electrode. - View Dependent Claims (9, 10)
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Specification