Self-balanced non-isolated hybrid modular DC-DC converter based on low duty cycle operation and sequential capacitors charging/discharging for medium voltage DC grids
1. An electrical converter, comprising:
- a first half-bridge sub-module;
a switch; and
a first capacitor, wherein;
the half-bridge sub-module is connected to the first capacitor, and the switch is connected to a terminal of the first half-bridge sub-module,the switch includes a plurality of insulated-gate bipolar transistors, andthe switch is configured to carry a sum of two currents during a first state, or a passive filter on a low voltage side is configured to provide a continuous current at the low voltage side.
An electrical converter is provided, comprising a first half-bridge sub-module, a switch, and a first capacitor. The half-bridge sub-module is connected to the first capacitor, and the switch is connected to a terminal of the first half-bridge sub-module. The switch includes a plurality of insulated-gate bipolar transistors. The insulated-gate bipolar transistors are serially connected with each other.
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Current AssigneeMitsubishi Electric Corporation
Sponsoring EntityMitsubishi Electric Corporation
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Current AssigneeOmron Corporation
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- 1. An electrical converter, comprising:
a first half-bridge sub-module; a switch; and a first capacitor, wherein; the half-bridge sub-module is connected to the first capacitor, and the switch is connected to a terminal of the first half-bridge sub-module, the switch includes a plurality of insulated-gate bipolar transistors, and the switch is configured to carry a sum of two currents during a first state, or a passive filter on a low voltage side is configured to provide a continuous current at the low voltage side.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
This application claims the benefit of priority from U.S. Provisional Application No. 62/593,473 filed Dec. 1, 2017.
High power direct current (DC)-DC converters are one of the main components in medium- to high-voltage DC grids, which are used to connect two different DC voltage levels. DC-DC converters can be classified into isolated and non-isolated. In isolated DC-DC converters, dual active, bridge-based DC-DC converters are the most common isolated DC-DC converter. In the case of high-voltage (HV) levels, switches with HV ratings are required, which necessitates using series-connected insulated gate bipolar transistors (IGBTs) to meet HV level requirements. Alternatively, multi-module DC-DC converters can be employed, but not without insulation challenges.
According to one non-limiting aspect of the present disclosure, an example embodiment of an electrical converter may include a half-bridge sub-module, a switch, and a capacitor. The half-bridge sub-module may be connected to the capacitor, and the switch may be connected to a terminal of the half-bridge sub-module. The electrical converter may be a self-balanced, bidirectional hybrid modular non-isolated DC-DC converter.
Additional features and advantages are described herein, and will be apparent from the following Detailed Description and the Figures.
For a proper understanding of this disclosure, reference should be made to the accompanying drawings, wherein:
The present disclosure describes various embodiments of a self-balanced, bidirectional, hybrid modular non-isolated DC-DC converter. In some embodiments, the self-balanced, bidirectional, hybrid modular non-isolated DC-DC converter may include half-bridge sub-modules (HB-SMs) and an HV switch. The HV switch may be implemented by a series connection of IGBTs having proper voltage sharing. The DC-DC converter may be operated with high conversion ratios. Based on the ratio of the voltages between the LV side (VdcL) and the HV side (VdcH), the number of HB-SMs (n) may be estimated where n>VdcH/VdcL.
In some embodiments, the proposed circuit may be considered a BC fed from the HV side. The BC may be operated with a low duty cycle, which may guarantee an efficient operation of the BC. During a turn-on period of the BC switch, the HB-SMs may be connected sequentially to the LV side. Based on the voltage level of the HB-SMs'"'"' capacitors and the voltage of the LV side, the power flow direction may be determined. Then, during a turn-off period of the BC switch, the LV side may be bypassed, while the HB-SMs'"'"' capacitors may be connected in series across the BC switch. Based on the total voltage of HB-SMs'"'"' capacitors, the power flow direction may be determined. The power flow control may be achieved by controlling a BC duty cycle through employing a simple proportional integral (PI) closed loop controller on the current at the HV side. The self-balanced bidirectional hybrid modular non-isolated DC-DC converter may provide self-balancing for HB-SMs'"'"' capacitors due to the sequential charging/discharging of HB-SMs'"'"' capacitors (i.e., sensorless voltage balancing techniques), operation with high conversion ratios, operating the BC with low duty cycles, which may ensure efficient operation, and bi-directional power flows.
In certain embodiments, the self-balancing, bidirectional, hybrid modular non-isolated DC-DC converter may be used for medium- to high-voltage, high-power applications. The configuration of the converter may provide a proper connection channel between two DC-link voltages with different voltage levels (i.e., low and high DC voltages, namely, VdcL and VdcH, respectively).
Based on the value employed by duty cycle D, the voltage across capacitors C1 to Cn may be higher or lower than the voltage across capacitor Cdc for a power flow direction from the HV side to the LV side, or from the LV side to the HV side, respectively (i.e., the proposed configuration may have the ability of bi-directional power flow between the HV side and the LV side).
In some embodiments, resistor Ri may be employed to reduce the expected in-rush current results from parallel connection of the capacitor Cdc at the LV side and the SMs'"'"' capacitances. The proper selection of the value of this resistance may limit the in-rush current with insignificant effects on the converter efficiency.
In certain embodiments, the turn-off period of Sx (DTs≤t<T) may be the second state. In this second state, the LV side may be bypassed by turning on the switch S′d, while SMs'"'"' capacitors C1 to Cn may be connected in series across the switch Sx, as illustrated in
Based on the aforementioned operational states, current ix may be a discontinuous current, as it may have a value during a first state while it drops to zero at the second state.
To have continuous current i1 at the LV side, a passive filter may be employed at the LV side, as illustrated in
The duty cycle of the switch Sx may be controlled to control the value and the direction of the power flow.
During a turn-on period of Sx, the SMs'"'"' capacitors may be discharged sequentially to provide their energy to the LV side through the limiting resistance Ri. As a result, current ix may have n exponential decays. Alternatively, inductor LH may be charged from the HV side, i.e., current i2 may increase linearly.
During a turn-off period of Sx, the SMs'"'"' capacitors may be connected in series across switch Sx to replenish their voltage again by charging through inductor LH. As a result, current i2 may decrease, while current ix may drop to zero. The employed filter at the LV side may be designed to have current i1 with a low ripple content, i.e., the average value of ix may equal i1, so that the level of ix during sequential discharging may approximately equal i1/D.
During a turn-on period of Sx, the SMs'"'"' capacitors may be charged sequentially from the LV side through the limiting resistance Ri. As a result, current ix may have n exponential decays. Alternatively, the inductor LH may discharge in the HV side, i.e., the current may decrease. In another embodiment, during a turn-off period of Sx, the SMs'"'"' capacitors may be connected in series across the switch Sx to start charging the inductor LH. As a result, the inductor current may increase, while current ix may drop to zero.
For the given voltage and current directions in
where r1 may be the internal resistance of inductance L1, as illustrated in
Equation 3 may be applied where the SMs'"'"' capacitances are series-connected across a BC output stage during a second state of operation.
By assuming that the involved capacitors are large enough, current ix during the sequential charging/discharging period may be considered as a constant at (i1/D) level with insignificant current ripples. Based on that, Equation 2 may be rewritten as Equation 4:
Equation 4 describes the relation between the current at the LV side and the duty cycle of switch Sx.
Based on Equation 4, the current may be zero when duty cycle D equals critical duty cycle Dcr, where the critical duty cycle may be given by:
If D>Dcr, current i1 may be positive, i.e., the power flow may be from the HV side to the LV side. Alternatively, if D<Dcr, current i1 may be negative, i.e., the power flow may be from the LV side to the HV side.
Based on Equation 5, the number of HB-SMs (n) may be selected for particular voltage levels to ensure operation within a certain range of the duty cycle.
As an example,
With respect to the design of the passive components of the converter, the second state of the operation, as illustrated in
Based on BC basics, inductor LH may be selected such that:
where fs=(1/TS) may be the switching frequency of an employed saw-tooth carrier, and ΔI may be the current peak-to-peak ripple magnitude. Based on the desired current ripple magnitude, suitable inductance at the HV side may be selected.
Alternatively, the SMs'"'"' capacitances may be connected in series across an output stage of the BC. If the capacitance of each SM is Ci, their equivalent capacitance may be Ci/n, which may be considered as the BC load in the second state. Based on that, Equation 7 may be used to choose the proper value of SMs'"'"' capacitances:
where ΔVSM may be the ripple voltage of the SMs'"'"' capacitors, while I2 may be the rated current of current i2. The capacitance may be chosen to ensure an insignificant voltage ripple. The constraint governing the value of capacitor voltage ripple is discussed in Equation 19, as discussed below.
With respect to the limiting resistance Ri, it may be selected to ensure an acceptable in-rush current peak when Cdc is connected in parallel with the HB-SMs'"'"' capacitances during the sequential charging/discharging period. In some embodiments, the power flow may be from the HV side to the LV side, and peak of current ix during the sequential charging/discharging period may be limited to (Ipk=(1+β)i1/D), as illustrated in
For a given current i1, Equation 8b, illustrated as a line in
The value of resistance Ri may be chosen such that the power dissipated in it is insignificant when compared with the power at the LV side to ensure high efficiency operation.
The average power of resistor Ri may be approximated by:
while the power at the LV side may be given by:
Using Equation 9 and Equation 10, Equation 11, illustrated as a line in
where α may be the desired ratio between the power dissipated in the resistor Ri to the power at the LV side, such as in Equation 12:
By plotting Equation 8b and Equation 11, the intersection point may determine a suitable value of Ri as well as a nominal value of the duty cycle for the given desired current level i1.
For example, if VdcH=25 kV, VdcL=10 kV, n=3 (i.e., Dcr=0.167), i1=+250 A (i.e., power flow may be from the HV side to the LV side), r1=0.01Ω, β=0.5, and α=0.005, the graphical representation for Equation 8b and Equation 11 is illustrated in
With respect to the capacitance at the LV side, for example, Cdc, it may be selected properly to ensure that the current at the end of each exponential decay in the sequential charging/discharging period is limited to ((1−β)i1/D) as illustrated in
where τ may be the equivalent time constant, which may equal RiCeq. The sequential charging/discharging may occur during time period DTs, which may be equally divided among the SMs, i.e., time period of each SM may be equal to DTs/n.
Based on Equation 14, at the end of the exponential decay, Equation 15 may be written as:
i.e., the equivalent capacitance may be given by:
Based upon Equation 13 and Equation 16, the capacitance Cdc may be calculated by Equation 17:
Based on Equation 17, the capacitance Ci may satisfy Condition 18:
Based on Equation 7 and Equation 17, the capacitor voltage ripples for SMs'"'"' capacitors should satisfy Condition 19:
Finally, L1 may be selected such that the current due to BC switching frequency fs is dampened at the LV side. To accomplish this, L1 may be selected such that the resonance between L1 and capacitance Cdc may occur at frequency fr, which may be lower and distinct from the BC switching frequency, for example, fr=fs/10. Thus, inductance L1 may given by:
The HB-SM switches may be clamped on the capacitor voltage level. Since the capacitor voltage may be higher or lower than the voltage of the LV side, such as according to the power flow direction, the design may be on the worst case, i.e., when the power flow is from the HV side to the LV side at the rated condition, where the voltage rating of each switch in the HB-SM may be higher than (VdcH/(1−DHL))/n, where DHL may be the duty cycle. If this voltage rating is available, a single Insulated Gate Bipolar Transistor (IGBT) may be employed for each switch in the HB-SMs. If not, each switch in the HB-SMs may be implemented by connecting a proper number of IGBTs in series with proper voltage sharing.
The involved switches in HB-SMs may have a high-pulsed current rating, as they may experience relatively high currents during the sequential connection of SMs to the LV side with a peak of (1+β)i1/D. As the duty cycle in case of power flow from the LV side to the HV side may be lower than the duty cycle in the other direction of the power flow, the design of switch current ratings may be based on the power flow from the LV side to the HV side, i.e., the pulsed current rating may higher than (1+β)i1/DLH for time DLHTS at the rated condition, where DLH may be the duty cycle when the power flow is from the LV side to the HV side.
In some embodiments, the high in-rush current may not pass through the lower switch in the HB-SM at the LV side, as it may carry current 12 during the second state (
The switch Sx may implemented as a series-connection of a certain number of IGBTs (i.e., h); as a result, the voltage rating of each IGBT may be higher than (VdcH/(1−DHL))/h.
With respect to the current rating, the switch Sx may carry the sum of two currents during the first state (
In certain embodiments, in order to reduce the pulsed current rating of the involved IGBTs, parallel modules for switches with high-pulsed current rating may be employed.
The closed loop controller for the proposed approach is illustrated in FIG. 7. The current of the HV side i2 may be measured and compared with its reference i2
A simulation model may be built for the proposed configuration, assuming a 2.5 MW (25 kV/10 kV) DC-DC transformer is used. The design steps are summarized below.
Based on Equation 5 above, the critical duty cycle may equal 0.167 assuming n=3.
For a rated power of 2.5 MW, the current at the LV side i1 may approximately equal +250 A (assuming the power flow is from the HV side to the LV side), r1=0.01, β=0.5, and a=0.005, based on
Based on Equation 6, the inductance at the HV side may be selected for a desired peak-peak ripple current magnitude ΔI. For a peak-to-peak current ripple magnitude of less than 40 A (i.e., 40%), an inductance of 0.12 H may be employed, assuming a switching frequency of 1 kHz.
Based on Equation 19, the peak-to-peak voltage ripple of the SMs'"'"' capacitors may be less than 34V. For a voltage ripples magnitude of 30V, using Equation 7, the suitable SM capacitance may equal approximately 1.73 mF, where I2≈100 A.
Based on Equation 17, the suitable capacitance at the LV side, Cdc, may equal 11 mF.
Finally, based on Equation 20, the inductance at the LV side L1 may equal 0.23 mH for a resonance frequency of 100 Hz. An internal resistance r1 of 0.01Ω may be assumed for L1.
The aforementioned extracted values may be defined in the model. The current at the HV side may be controlled to be 100 A for 0≤t<2 s, then −100 A for 2 s≤t<3 s. A conventional PI-based current controller may be employed with constants (kp=1×10−4 and ki=1×10−3) to generate the suitable duty cycle. The duty cycle may then be sent to the sequential operation control block, as illustrated in
The bi-directional, hybrid, modular non-isolated DC-DC converter may be effectively used in connecting two different DC voltage levels in medium- to high-voltage DC grids. The capacitors of involved HB-SMs in the proposed configurations may be self-balancing, with no need for any voltage/current measurement for capacitor voltage balancing issues. The suggested approach may ensure operating the boost converter under low duty cycle efficiently. The value of duty cycle may be the key for controlling the power flow direction, where if the duty cycle is higher than the critical value, the power flow may be from the HV side to the LV side and vice versa. The critical duty cycle may depend on the HV and LV levels, as well as a number of employed HB-SMs. All governing equations have been provided for a better explanation of the converter operational concept, as well as a full design of the converter components. A closed loop controller for the suggested architecture is also proposed. The closed loop controller may be used where the current at the HV side controls the power demand and direction. Finally, simulation results have been provided to validate the design equations and the proposed concepts.
The features, structures, or characteristics of certain embodiments described throughout this specification may be combined in any suitable manner in one or more embodiments. For example, the usage of the phrases “certain embodiments,” “some embodiments,” “other embodiments,” or other similar language, throughout this specification refers to the fact that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present invention. Thus, appearance of the phrases “in certain embodiments,” “in some embodiments,” “in other embodiments,” or other similar language, throughout this specification does not necessarily refer to the same group of embodiments, and the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
One having ordinary skill in the art will readily understand that certain embodiments discussed above may be practiced with steps in a different order, and/or with hardware elements in configurations that are different from those which are disclosed. Therefore, it would be apparent to those of skill in the art that certain modifications, variations, and alternative constructions would be apparent, while remaining within the spirit and scope of the invention. In order to determine the metes and bounds of the invention, therefore, reference should be made to the appended claims.
- AC Alternating Current
- DC Direct Current
- HB-SM Half-bridge Sub-module
- HV High Voltage
- IGBT Insulated Gate Bipolar Transistor
- LV Low Voltage
- PI Proportional Integral
- SM Sub-module