Dead-time conduction loss reduction for buck power converters

• US 10,644,601 B2
• Filed: 04/02/2019
• Issued: 05/05/2020
• Est. Priority Date: 06/22/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Pao, Chia-Cheng, Chen, Chu Fu, Wang, Chih-Hua
• Primary Examiner(s): Zhang, Jue
• Assistant Examiner(s): Dang, Trinh Q
• Application Number:
  US16/372,823
• Publication Number:
  US 20190393785A1
• Time in Patent Office: 399 Days
• CPC Class Codes: H02M 1/0038 Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
• CPC Class Codes: H02M 1/0051 Diode reverse recovery losses
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Various embodiments of the present application are directed towards a buck converter circuit including a controller circuit. In some embodiments, the buck converter circuit includes a first switching device, a second switching device, an inductor, and a controller. The inductor is electrically coupled to a node at which a source/drain terminal of the first switching device and a source/drain terminal of the second switching device are electrically coupled. The controller is configured to alternatingly change the first switching device between ON and OFF, and further configured to alternatingly change the second switching device between ON and OFF. The first switching device is OFF while the second switching device is ON. The first switching device is partially ON immediately before or after the second switching device transitions between ON and OFF.

Claims

1. A buck converter circuit comprising:

a first switching device;

a second switching device;

an inductor electrically coupled to a node at which a first source/drain of the first switching device and a first source/drain of the second switching device are electrically coupled; and

a controller configured to alternatingly change the first switching device between ON and OFF, and further configured to alternatingly change the second switching device between ON and OFF, wherein the first switching device is OFF while the second switching device is ON, wherein the first switching device is partially ON immediately before or after the second switching device transitions between ON and OFF, wherein a gate of the first switching device is biased with a threshold voltage while ON and is biased with a subthreshold voltage while partially ON, wherein the subthreshold voltage is non-zero, and wherein an absolute value of the subthreshold voltage is greater than or equal to half of an absolute value of the threshold voltage.

2. The buck converter circuit according to claim 1, wherein the first switching device comprises a second source/drain region, wherein the first and second source/drain regions of the first switching device are disposed within a substrate on opposite sides of the gate of the first switching device, and wherein a conductive channel forms within the substrate directly beneath the gate of the first switching device and between the first and second source/drain regions of the first switching device when the first switching device is partially ON.

3. The buck converter circuit according to claim 1, wherein the first switching device is partially ON immediately before the second switching device transitions from OFF to ON.

4. The buck converter circuit according to claim 1, wherein the first switching device is partially ON immediately after the second switching device transitions from ON to OFF.

5. The buck converter circuit according to claim 1, the controller further comprising:

a loss-prevention circuit electrically coupled to the gate of the first switching device and the gate of the second switching devices, wherein the loss-prevention circuit is configured to determine a first time frame immediately before the second switching device transitions from OFF to ON and a second time frame immediately after the second switching device transitions from ON to OFF, and wherein the loss-prevention circuit turns the first switching device partially ON during the first and second time frames.

6. The buck converter circuit according to claim 5, wherein durations of the first and second time frames are respectively defined by a period in which both the first and second switching devices are OFF, and wherein the first switching device is partially ON for an entirety of the durations.

7. The buck converter circuit according to claim 6, wherein during the first and second time frames the buck converter comprises:

a first current path between a second source/drain of the first switching device and the node, wherein the first current path conducts through an internal diode of the first switching device; and

a second current path between the second source/drain of the first switching device and the node, wherein the second current path conducts through a conductive channel formed within the first switch device, and wherein the first and second current paths are in parallel.

8. A buck converter circuit comprising:

a first switching device;

a second switching device;

an inductor, wherein the first and second switching devices and the inductor are coupled at a node;

a controller configured to apply a first pulse train and a second pulse train respectively to gate terminals of the first and second switching devices to alternatingly change the first and second switching devices between a first state and a second state;

a loss-prevention circuit electrically coupled to the gate terminals of the first and second switching devices and configured to bias the gate terminal of the first switching device with a voltage less than a threshold voltage of the first switching device while transitioning between the first and second states, wherein the loss-prevention circuit comprises;

a third switching device electrically coupled to ground and the gate terminal of the first switching device;

a pullup resistor electrically coupled to a power supply rail and the gate terminal of the first switching device; and

a level shifter electrically coupled from the gate terminal of the first switching device to a gate terminal of the third switching device.

9. The buck converter circuit according to claim 8, wherein the first switching device is ON and the second switching device is OFF at the first state, and wherein the first switching device is OFF and the second switching device is ON at the second state.

10. The buck converter circuit according to claim 8, wherein the loss-prevention circuit is further configured to:

detect when the first and second switching devices are in a third state, wherein the third state occurs when transitioning from the first state to the second state or when transitioning from the second state to the first state, and wherein the first and second switching devices are OFF in the third state; and

augment the first pulse train during the third state to partially turn ON the first switching device.

11. The buck converter circuit according to claim 8, wherein the first switching device is an n-channel metal-oxide-semiconductor (MOS) device, and wherein the second switching device is a p-channel MOS device.

12. The buck converter circuit according to claim 10, wherein during the third state the buck converter comprises:

a first current path between a power supply rail and the node;

a second current path between a source/drain terminal of the first switching device and the node, wherein the second current path conducts through an internal diode of the first switching device; and

a third current path between the source/drain terminal and the node, wherein the third current path conducts through a conductive channel formed within the first switch device, and wherein the third and second current paths are in parallel.

13. The buck converter circuit according to claim 12, wherein the first and second current paths respectively occur along an NPN junction within a substrate.

14. The buck converter circuit according to claim 12, wherein during the third state current flows through the first, second, and third current paths.

15. A method comprising:

applying a first pulse train to a first switching device to alternatingly change the first switching device between ON and OFF, such that the first switching device is in a triode mode while ON;

applying a second pulse train to a second switching device to alternatingly change the second switching device between ON and OFF, wherein the second switching device is OFF while the first switching device is ON and the first switching device is OFF while the second switching device is ON;

charging an inductor from a node at which source/drain regions respectively of the first and second switching devices are electrically coupled, wherein the charging is performed while the second switching device is ON;

discharging the inductor while the second switching device is OFF; and

biasing a gate of the first switching device with a subthreshold voltage less than a threshold voltage of the first switching device immediately after detecting the first pulse train is low and the second pulse train is high, wherein biasing the first switching device with the subthreshold voltage places the first switching device in a subthreshold mode, such that the subthreshold mode is between a cutoff mode of the first switching device and the triode mode of the first switching device, and wherein the subthreshold voltage is non-zero.

16. The method according to claim 15, wherein the first pulse train has a first duty cycle and the second pulse train has a second duty cycle greater than the first duty cycle, and wherein the first pulse train has a phase offset relative to the second pulse train.

17. The method according to claim 15, wherein the first switching device is an n-channel metal-oxide-semiconductor (MOS) device, and wherein the second switching device is a p-channel MOS device.

18. The method according to claim 16, immediately after detecting the first and second pulse trains are respectively low and high the method further comprises:

forming a conductive channel within the first switching device, wherein a weak-inversion current flows through the conductive channel to the node.

19. The method according to claim 16, wherein biasing the gate of the first switching device with the subthreshold voltage less than the threshold voltage forms a conductive channel between a first source/drain region and a second source/drain region of the first switching device, wherein the conductive channel is directly beneath the gate of the first switching device.

20. The method according to claim 18, wherein the weak-inversion current is in parallel with a current flowing through an internal diode of the first switching device.