Low power radio frequency signal detector

• US 10,644,663 B1
• Filed: 12/14/2018
• Issued: 05/05/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Shrivastava, Kumar Anurag, Nasum, Sreeram Subramanyam
• Primary Examiner(s): Cox, Cassandra F
• Application Number:
  US16/220,357
• Publication Number:
  US 20200136576A1
• Time in Patent Office: 508 Days
• Field of Search: None
• CPC Class Codes: G05F 1/595 semiconductor devices connected in series
• CPC Class Codes: H03F 2203/45302 the common gate stage of a cascode dif amp being controlled
• CPC Class Codes: H03F 2203/45394 the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
• CPC Class Codes: H03F 2203/45544 the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence

Abstract

A low power radio frequency (RF) signal detector comprising a set of transistors, a bias input circuitry configured to apply bias to each of the set of transistors, and a differential signal input circuitry configured to apply a pair of differential signals to the set of transistors, wherein the pair of differential signals increases or decreases bias applied to the set of transistors to achieve low power, high frequency RF signal detection.

Claims

1. A pull down circuitry comprising:

a first set of transistors;

a bias input circuitry coupled to the first set of transistors; and

a differential signal input circuitry coupled to the first set of transistors;

wherein the bias input circuitry is configured to apply bias to each of the first set of transistors and the differential signal input circuitry is configured to apply a pair of differential signals to the first set of transistors to increase or decrease the bias applied by the bias input circuitry.

2. The pull down circuitry of claim 1,

wherein the bias input circuitry is configured to apply bias to each of the first set of transistors through the each transistor'"'"'s gate.

3. The pull down circuitry of claim 1,

wherein the differential signal input circuitry is configured to apply the pair of differential signals to each of the first set of transistors through the each transistor'"'"'s gate and source.

4. The pull down circuitry of claim 3,

wherein the first set of transistors comprises a first pair of transistors, and

the differential signal input circuitry is configured to apply a signal of the pair of the differential signals to one transistor of the first pair of transistors through the one transistor'"'"'s gate and to the other transistor of the first pair of the transistors through the other transistor'"'"'s source, and apply another signal of the pair of the differential signals to the one transistor of the first pair of transistors through the one transistor'"'"'s source and to the other transistor of the first pair of the transistors through the other transistor'"'"'s gate.

5. The pull down circuitry of claim 1,

wherein the bias applied by the bias input circuitry is less than threshold voltage of each of the first set of transistors and

the pair of differential signals applied by the differential signal input circuitry comprises alternating signals and increases and decreases the bias above and below the threshold voltage.

6. A radio frequency signal detector comprising:

a first set of transistors;

a bias input circuitry coupled to the first set of transistors and configured to apply bias to each of the first set of transistors;

a differential signal input circuitry coupled to the first set of transistors and configured to apply a pair of differential signals to the first set of transistors to increase or decrease the bias applied by the bias input circuitry;

a comparator configured to lower voltage output when the pair of differential signals is applied to the first set of transistors; and

an output generator configured to generate an output signal reflective of the voltage output of the comparator when the voltage output from the comparator is lowered,

wherein transistors of the first set of transistors are configured to turn on and off alternatively when the bias applied by the bias input circuitry is increased or decreased by the application of the pair of differential signals by the differential signal input circuitry, and the comparator is configured to lower the voltage output when any of the first set of transistors is turned on.

7. The radio frequency signal detector of claim 6,

wherein the comparator comprises a PMOS transistor, and

wherein the PMOS transistor is configured to output a current of a predetermined value, and the voltage output of the comparator is lowered when the current of the first set of transistors is higher than the predetermined value.

8. The radio frequency signal detector of claim 7,

wherein the first set of transistors comprises a pair of NMOS transistors, and

wherein the pair of NMOS transistors is configured to output a current higher than the predetermined value when any of the pair of the NMOS transistors is turned on.

9. The radio frequency signal detector of claim 6,

wherein the output generator comprises a PMOS transistor and a resistor coupled to the PMOS transistor'"'"'s drain,

the comparator is configured to apply its voltage output to a gate of the PMOS transistor of the output generator, and

the PMOS transistor is configured to turn on to apply current to the resistor when the voltage output of the comparator is lowered.

10. The radio frequency signal detector of claim 9,

wherein the output signal generated by the output generator comprises voltage over the resistor.

11. The radio frequency signal detector of claim 6,

wherein the first set of transistors comprises a pair of NMOS transistors, and

wherein the bias input circuitry is configured to apply bias to each of the pair of NMOS transistors through the each NMOS transistor'"'"'s gate.

12. The radio frequency signal detector of claim 11,

wherein the differential signal input circuitry is configured to apply the pair of differential signals to the each of the pair of NMOS transistors through the each NMOS transistor'"'"'s gate and source.

13. The radio frequency signal detector of claim 12,

wherein the differential signal input circuitry is configured to apply a signal of the pair of the differential signals to one NMOS transistor of the pair of NMOS transistors through the one NMOS transistor'"'"'s gate and to the other NMOS transistor of the pair of the NMOS transistors through the other NMOS transistor'"'"'s source, and apply another signal of the pair of the differential signals to the one NMOS transistor of the pair of NMOS transistors through the one NMOS transistor'"'"'s source and to the other NMOS transistor of the pair of the NMOS transistors through the other NMOS transistor'"'"'s gate.

14. The radio frequency signal detector of claim 13,

wherein the bias applied by the bias input circuitry is less than threshold voltage of each of the pair of NMOS transistors, and

the pair of differential signals applied by the differential signal input circuitry comprises alternating signals and increases and decreases the bias above and below the threshold voltage.

15. The radio frequency signal detector of claim 6,

wherein the pair of differential signals comprises a pair of differential signals corresponding to a radio frequency signal received by the radio frequency signal detector.

16. A digital isolator comprising,

a transmitter configured to transmit a radio frequency signal;

a receiver configured to receive the radio frequency signal transmitted by the transmitter; and

an isolation barrier configured to transmit the radio frequency signal transmitted by the transmitter to the receiver through a capacitor,

wherein the receiver comprises,

a first set of transistors;

a bias input circuitry coupled to the first set of transistors and configured to apply bias to each of the first set of transistors;

a differential signal input circuitry coupled to the first set of transistors and configured to apply a pair of differential signals to the first set of transistors to increase or decrease the bias applied by the bias input circuitry;

a comparator configured to lower voltage output when the pair of differential signals is applied to the first set of transistors; and

an output generator configured to generate an output signal reflective of the voltage output of the comparator when the voltage output from the comparator is lowered,

wherein transistors of the first set of transistors are configured to turn on and off alternatively when the bias applied by the bias input circuitry is increased or decreased by the application of the pair of differential signals by the differential signal input circuitry, and the comparator is configured to lower the voltage output when any of the first set of transistors is turned on.

17. The digital isolator of claim 16,

wherein the comparator comprises a PMOS transistor, and the first set of transistors comprises a pair of NMOS transistors, and

wherein the pair of NMOS transistors is configured to output a current higher than a current of the PMOS transistor of the comparator when any of the pair of NMOS transistors is turned on.

18. The digital isolator of claim 17,

wherein the output generator comprises a PMOS transistor and a resistor coupled to a drain of the PMOS transistor of the output generator,

the comparator is configured to apply its voltage output to a gate of the PMOS transistor of the output generator, and

the PMOS transistor is configured to turn on to apply current to the resistor when the voltage output of the comparator is lowered.

19. The digital isolator of claim 18,

wherein the output signal generated by the output generator comprises voltage over the resistor.

20. The digital isolator of claim 18 further comprises,

a second bias input circuitry configured to apply bias to a source of the PMOS transistor of the comparator and to a source of the PMOS transistor of the output generator.

21. The digital isolator of claim 16,

wherein the pair of differential signals comprises a pair of differential signals corresponding to the radio frequency signal received by the receiver.