Switched resistance device with reduced sensitivity to parasitic capacitance

• US 10,644,675 B2
• Filed: 10/02/2017
• Issued: 05/05/2020
• Est. Priority Date: 10/02/2017
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Ganta, Saikrishna, Chen, Man-Chia, Ezekwe, Chinwuba
• Primary Examiner(s): Donovan, Lincoln D
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US15/722,717
• Publication Number:
  US 20190103856A1
• Time in Patent Office: 946 Days
• Field of Search: None
• CPC Class Codes: H03H 11/04 Frequency selective two-port networks
• CPC Class Codes: H03H 19/008 with variable switch closing time

Abstract

A stacked switched resistance device has been developed. The stacked switched resistance device includes a plurality of segments connected in series. Each segment includes a resistor including an inherent parasitic capacitance, and a switch connected in series with the resistor, the switch being configured to connect and disconnect the resistor from the plurality of segments in response to a predetermined clock signal. An effective resistance of the stacked switched resistance device exceeds another effective resistance of at least one resistor with an equivalent inherent resistance that is connected in series to a single switch configured to connect and disconnect the at least one resistor in response to the predetermined clock signal.

Claims

1. A stacked switched resistance device comprising:

a clock source configured to generate a predetermined clock signal at a predetermined frequency and a predetermined duty cycle; and

a plurality of segments connected in series and configured to produce a first effective resistance, each segment comprising;

a resistor including an inherent resistance and an inherent parasitic capacitance; and

a transistor connected in series with the resistor, the transistor having a control terminal operatively connected to clock source and configured to receive the predetermined clock signal, the transistor being configured to operate as a switch to connect and disconnect a current flow through the resistor in response to the predetermined clock signal,

wherein the first effective resistance of the stacked switched resistance device exceeds a second effective resistance of at least one resistor that is connected in series to a single transistor configured to connect and disconnect the at least one resistor in response to the predetermined clock signal, the at least one resistor having an inherent resistance that is equal to a sum of the inherent resistances of the resistors in the plurality of segments and an inherent parasitic capacitance that is equal to a sum of the inherent parasitic capacitances of the resistors in the plurality of segments.

2. The stacked switched resistance device of claim 1 wherein the clock source is configured to generate the predetermined clock signal to operate each transistor in the plurality of segments simultaneously.

3. The stacked switched resistance device of claim 1 wherein the plurality of segments further comprises two segments.

4. The stacked switched resistance device of claim 1 wherein the plurality of segments further comprises thirty segments.

5. The stacked switched resistance device of claim 1 wherein the resistor in each segment of the plurality of segments has an equal resistance value.

6. The stacked switched resistance device of claim 5 wherein the first effective resistance (R_eff,total) corresponds to:

7. The stacked switched resistance device of claim 6 wherein an effect of the sum of the inherent parasitic capacitances C_p on the first effective resistance is reduced by a factor of N² for the number of the plurality of segments.

8. The stacked switched resistance device of claim 1 wherein the plurality of segments are formed in an integrated circuit.

9. A filter circuit comprising:

a stacked switched resistance device comprising;

an input configured to receive a signal to be filtered in the filter circuit;

an output;

a clock source configured to generate a predetermined clock signal at a predetermined frequency and a predetermined duty cycle; and

a plurality of segments connected in series between the input and the output and configured to produce a first effective resistance, each segment comprising;

a resistor including an inherent resistance and an inherent parasitic capacitance; and

a transistor connected in series with the resistor, the transistor having a control terminal operatively connected to clock source and configured to receive the predetermined clock signal, the transistor being configured to operate as a switch to connect and disconnect a current flow through the resistor in response to the predetermined clock signal,

wherein the first effective resistance of the stacked switched resistance device exceeds a second effective resistance of at least one resistor that is connected in series to a single transistor configured to connect and disconnect the at least one resistor in response to the predetermined clock signal, the at least one resistor having an inherent resistance that is equal to a sum of the inherent resistances of the resistors in the plurality of segments and an inherent parasitic capacitance that is equal to a sum of the inherent parasitic capacitances of the resistors in the plurality of segments; and

a filter capacitor connected to the output of the stacked switched resistance device.

10. The filter circuit of claim 9 wherein the clock source is configured to generate the predetermined clock signal to operate each transistor in the plurality of segments simultaneously.

11. The filter circuit of claim 9 wherein the plurality of segments in the stacked switched resistance device further comprises two segments.

12. The filter circuit of claim 9 wherein the plurality of segments in the stacked switched resistance device further comprises thirty segments.

13. The filter circuit of claim 9 wherein the resistor in each segment of the plurality of segments in the stacked switched resistance device has an equal resistance value.

14. The filter circuit of claim 13 wherein the first effective resistance (R_eff,total) of the stacked switched resistance device corresponds to:

15. The filter circuit of claim 14 wherein an effect of the sum of the inherent parasitic capacitances C_p on the first effective resistance is reduced by a factor of N² for the number of the plurality of segments.

16. The filter circuit of claim 9 wherein the filter circuit is a low-pass filter.