Level shift circuit

• US 10,644,679 B2
• Filed: 01/16/2019
• Issued: 05/05/2020
• Est. Priority Date: 02/22/2018
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Takeda, Koichi
• Primary Examiner(s): Nguyen, Long
• Application Number:
  US16/249,502
• Publication Number:
  US 20190260360A1
• Time in Patent Office: 475 Days
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

A level shift circuit includes a pulse signal generation unit generating first and second pulse signals with respect to an input signal, a first level conversion unit converting the first pulse signal at a first voltage to a third pulse signal at a second voltage, a second level conversion unit converting the second pulse signal at the first voltage to a fourth pulse signal at the second voltage, and a flip flop circuit making an output signal at the second voltage rise according to the third pulse signal, and making the output signal at the second voltage fall according to the fourth pulse signal. The pulse signal generation unit compares the input signal with the output signal of the flip flop circuit, and generates the first pulse signal when the input signal rises and the second pulse signal when the input signal falls, based on a non-matching comparison result.

Claims

1. A level shift circuit comprising:

a pulse signal generation unit that generates first and second pulse signals with respect to an input signal;

a first level conversion unit that converts the first pulse signal at a first voltage to a third pulse signal at a second voltage;

a second level conversion unit that converts the second pulse signal at the first voltage to a fourth pulse signal at the second voltage; and

a flip flop circuit that makes an output signal at the second voltage rise according to the third pulse signal and makes the output signal at the second voltage fall according to the fourth pulse signal,

wherein when the input signal rises, the pulse signal generation unit compares the input signal with the output signal of the flip flop circuit, and generates the first pulse signal based on a non-matching comparison result, and

wherein when the input signal falls, the pulse signal generation unit compares the input signal with the output signal of the flip flop circuit, and generates the second pulse signal based on the non-matching comparison result.

2. The level shift circuit according to claim 1,

wherein the pulse signal generation unit includes:

a third level conversion unit that converts the output signal at the second voltage to the first voltage;

a logical sum circuit that outputs the logical sum operation result of the input signal and the output signal from the third level conversion unit;

a first AND circuit that outputs, as the first pulse signal, the AND logical operation result of the input signal and the logical sum operation result; and

a second AND circuit that outputs, as the second pulse signal, the AND logical operation result of the inversion signal of the input signal and the logical sum operation result.

3. The level shift circuit according to claim 1,

wherein each of the first and second level conversion units includes:

a resistance element that is coupled between the second voltage and an internal node;

a first MOS transistor that is provided between the internal node and a third voltage and has a gate receiving the respective of the first pulse signal at the first voltage and the second pulse signal at the first voltage;

a second MOS transistor that is coupled between the second voltage and an output node and has a gate coupled to the internal node; and

a third MOS transistor that is coupled between the output node and the third voltage and has a gate coupled to the internal node.

4. The level shift circuit according to claim 1,

wherein each of the first and second level conversion units includes:

a first MOS transistor that is coupled between the second voltage and an internal node and has a gate coupled to the internal node;

a second MOS transistor that is coupled between the second voltage and an output node so as to form a current mirror circuit together with the first MOS transistor;

a third MOS transistor that is provided between the internal node and a third voltage and has a gate receiving the respective of the first pulse signal at the first voltage and the second pulse signal at the first voltage; and

a fourth MOS transistor that is coupled between the output node and the third voltage and has a gate receiving the respective of the inversion signal of the first pulse signal and the inversion signal of the second pulse signal.

5. The level shift circuit according to claim 1,

wherein the flip flop circuit includes a state detection circuit that compares an internal signal held according to the input of the third and fourth pulse signals with the output signal to output a state signal indicating the state of the internal signal at the second voltage,

wherein when the input signal rises, the pulse signal generation unit compares the input signal with the output signal of the flip flop circuit, and generates the first pulse signal based on a non-matching comparison result or the state signal, and

wherein when the input signal falls, the pulse signal generation unit compares the input signal with the output signal of the flip flop circuit, and generates the second pulse signal based on the non-matching comparison result or the state signal.

6. The level shift circuit according to claim 5,

wherein the state detection circuit further includes a latch circuit that holds the internal signal according to the inputs of the third and fourth pulse signals, and

wherein the logical threshold value of the latch circuit and the logical threshold value of the state detection circuit are different from each other.

7. The level shift circuit according to claim 5,

wherein the pulse signal generation unit includes:

a third level conversion unit that converts the output signal at the second voltage to the first voltage;

a fourth level conversion unit that converts the state signal at the second voltage to the first voltage;

a logical sum circuit that outputs the logical sum operation result of the input signal and the output signal from the third level conversion unit;

an OR circuit that outputs the OR logical operation result of the output signal of the logical sum circuit and the output signal of the fourth level conversion unit;

a first AND circuit that outputs, as the first pulse signal, the AND logical operation result of the input signal and the output signal of the OR circuit; and

a second AND circuit that outputs, as the second pulse signal, the AND logical operation result of the inversion signal of the input signal and the output signal of the OR circuit.

8. The level shift circuit according to claim 1,

wherein the pulse signal generation unit includes:

a third level conversion unit that converts the output signal at the second voltage to the first voltage;

a fourth level conversion unit that converts the inversion signal of the output signal at the second voltage to the first voltage;

a logical sum circuit that outputs the logical sum operation result of the input signal and the output signal from the third level conversion unit;

a first AND circuit that outputs the AND logical operation result of the output signal of the third level conversion unit and the inversion signal of the output signal of the fourth level conversion unit;

an OR circuit that outputs the OR logical operation result of the output signal of the first AND circuit and the output signal of the logical sum circuit;

a second AND circuit that outputs, as the first pulse signal, the AND logical operation result of the input signal and the output signal of the OR circuit; and

a third AND circuit that outputs, as the second pulse signal, the AND logical operation result of the inversion signal of the input signal and the output signal of the OR circuit.

9. The level shift circuit according to claim 1,

wherein the pulse signal generation unit includes:

a third level conversion unit that converts the output signal at the second voltage to the first voltage;

a fourth level conversion unit that converts the inversion signal of the output signal at the second voltage to the first voltage;

a first AND circuit that outputs the AND logical operation result of the inversion signal of the input signal and the output signal of the third level conversion unit;

a second AND circuit that outputs the AND logical operation result of the input signal and the inversion signal of the output signal of the fourth level conversion unit;

an OR circuit that outputs the OR logical operation result of the output signal of the first AND circuit and the output signal of the second AND circuit;

a third AND circuit that outputs, as the first pulse signal, the AND logical operation result of the input signal and the output signal of the OR circuit; and

a fourth AND circuit that outputs, as the second pulse signal, the AND logical operation result of the inversion signal of the input signal and the output signal of the OR circuit.

10. The level shift circuit according to claim 1,

wherein the pulse signal generation unit includes:

a selector that outputs one of the input signal and the inversion signal of the input signal according to the output signal;

a first AND circuit that outputs, as the first pulse signal, the AND logical operation result of the input signal and the inversion signal of the signal selected by the selector; and

a second AND circuit that outputs, as the second pulse signal, the AND logical operation result of the input signal and the inversion signal of the signal selected by the selector.

11. The level shift circuit according to claim 10,

wherein the selector includes:

a first switch that selects the input signal according to the input of the output signal; and

a second switch that selects the inversion signal of the input signal according to the input signal of the inversion signal of the output signal.

12. The level shift circuit according to claim 11,

wherein the pulse signal generation unit includes:

a first inverter that outputs the inversion signal of the input signal;

second and third inverters that are coupled in series to output a signal having the same phase as the input signal;

a first MOS transistor that has a source coupled to the second and third inverters, a gate receiving the input of the output signal, and a drain coupled to an output node; and

a second MOS transistor that has a source coupled to the first inverter, a gate receiving the input of the inversion signal of the output signal, and a drain coupled to the output node.

13. The level shift circuit according to claim 12,

wherein each of the first inverter, the second inverter, and the third inverter is configured of a CMOS inverter of a P-channel MOS transistor and an N-channel MOS transistor, and

wherein the driving ability of the N-channel MOS transistor is set higher than the driving of the P-channel MOS transistor with respect to the input signal.

14. The level shift circuit according to claim 2, wherein the logical sum circuit corresponds to an exclusive logical sum circuit that outputs the exclusive logical sum operation result of the input signal and the output signal from the third level conversion unit.