Self-clocking sampler with reduced metastability

• US 10,644,686 B2
• Filed: 12/02/2019
• Issued: 05/05/2020
• Est. Priority Date: 08/31/2017
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Poulton, John W., Kudva, Sudhir Shrikantha, Tell, Stephen G., Wilson, John Michael
• Primary Examiner(s): O Neill, Patrick
• Application Number:
  US16/700,839
• Publication Number:
  US 20200106428A1
• Time in Patent Office: 155 Days
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: H02M 3/1563 without using an external clock H02M3/158 takes precedence
• CPC Class Codes: H03K 19/0966 Self-timed logic
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/356191 with synchronous operation
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first voltage level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second voltage level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage levels, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage levels transitioning from the second level to the first level, the detection circuit transitions the output signal from the first voltage level to the second voltage level.

Claims

1. A self-clocked sampler system, comprising:

a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals;

a detection circuit that is coupled to the sampler circuit and configured to;

pre-charge the sampled signals when the clock signal is at a second voltage level;

detect a voltage level of a first one of the sampled signals by a first threshold adjusted inverter, wherein a threshold voltage of the first threshold adjusted inverter is entirely outside of a transition voltage range of the sampler circuit;

detect a voltage level of a second one of the sampled signals by a second threshold adjusted inverter, wherein a threshold voltage of the second threshold adjusted inverter is entirely outside of the transition voltage range of the sampler circuit; and

combine the detected voltage levels of the first and second sampled signals to transition an output signal from the first level to the second level in response to one of the detected voltage levels of the first and second sampled signals transitioning from the second voltage level to the first voltage level; and

a feedback circuit configured to receive the output signal and generate the clock signal.

2. The system of claim 1, wherein the feedback circuit comprises an even number of inverters coupled in series.

3. The system of claim 2, wherein a delay of at least one inverter in the even number of inverters is programmable.

4. The system of claim 2, wherein an output of a first inverter in the even number of inverters is a clock output signal.

5. The system of claim 1, wherein the threshold voltage is lower than the transition voltage range.

6. The system of claim 5, wherein the first threshold adjusted inverter is coupled to a first one of the sampled signals and the second threshold adjusted inverter is coupled to a second one of the sampled signals and outputs of the first and second threshold adjusted inverters are coupled to inputs of a NOR gate to produce the output signal.

7. The system of claim 1, wherein the threshold voltage is higher than the transition voltage range.

8. The system of claim 7, wherein the first threshold adjusted inverter is coupled to a first one of the sampled signals and the second threshold adjusted inverter is coupled to a second one of the sampled signals and outputs of the first and second threshold adjusted inverters are coupled to inputs of a NAND gate to produce the output signal.

9. The system of claim 1, wherein the feedback circuit comprises one or more flip-flops coupled in series.

10. The system of claim 1, wherein a frequency of the clock signal varies.

11. The system of claim 1, wherein the transition voltage range bounds a metastability state of the sampled signals.

12. The system of claim 1, wherein one of the detected voltage levels of the first and second sampled signals is a voltage comparison output signal.

13. A computer-implemented method, comprising:

pre-charging sampled signals, by a detection circuit, when a clock signal is at a second voltage level;

sampling input signals, by a sampler circuit, when the clock signal is at a first voltage level to drive the sampled signals;

detecting a voltage level of a first one of the sampled signals by a first threshold adjusted inverter, wherein a threshold voltage of the first threshold adjusted inverter is entirely outside of a transition voltage range of the sampler circuit;

detecting a voltage level of a second one of the sampled signals by a second threshold adjusted inverter, wherein a threshold voltage of the second threshold adjusted inverters is entirely outside of the transition voltage range of the sampler circuit;

combining, by the detection circuit, the detected voltage levels of the first and second sampled signals to transition an output signal from the first voltage level to the second voltage level in response to one of the detected voltage levels of the first and second sampled signals transitioning from the second voltage level to the first voltage level; and

generating the clock signal by a feedback circuit that receives the output signal.

14. The computer-implemented method of claim 13, wherein the feedback circuit comprises an even number of inverters coupled in series.

15. The computer-implemented method of claim 14, wherein a delay of at least one inverter in the even number of inverters is programmable.

16. The computer-implemented method of claim 14, wherein an output of a first inverter in the even number of inverters is a clock output signal.

17. The computer-implemented method of claim 13, wherein the threshold voltage is lower than the transition voltage range.

18. The computer-implemented method of claim 13, wherein the threshold voltage is higher than the transition voltage range.

19. The computer-implemented method of claim 13, wherein the transition voltage range bounds a metastability state of the sampled signals.

20. The computer-implemented method of claim 13, wherein one of the detected voltage levels of the first and second sampled signals is a voltage comparison output signal.