Lower voltage switching of current mode logic circuits

• US 10,644,699 B2
• Filed: 05/31/2018
• Issued: 05/05/2020
• Est. Priority Date: 05/31/2018
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Finn, Steven Ernest
• Primary Examiner(s): Chen, Patrick C
• Application Number:
  US15/993,725
• Publication Number:
  US 20190372571A1
• Time in Patent Office: 705 Days
• CPC Class Codes: H03K 19/001 in bipolar transistor circuits
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/017554 using a combination of bipolar and field effect transistors [BIFET]
• CPC Class Codes: H03K 19/09448 in combination with bipolar transistors [BIMOS]

Abstract

A circuit includes a first transistor comprising a first control input and first and second current terminals, the first control input coupled to receive a first input control signal, and the first current terminal coupled to a first power supply node. The circuit also includes a first resistor coupled to the first control input of the first transistor, a first capacitor coupled between the second current terminal of the first transistor and the first resistor and a second transistor comprising a second control input and third and fourth current terminals, the third current terminal coupled to the first resistor and to the first capacitor.

Claims

1. A circuit, comprising:

a first transistor comprising a first control input and first and second current terminals, the first control input coupled to receive a first input control signal, and the first current terminal coupled to a first power supply node;

a first resistor coupled to the first control input of the first transistor;

a first capacitor coupled between the second current terminal of the first transistor and the first resistor;

a second transistor comprising a second control input and third and fourth current terminals, the third current terminal coupled to the first resistor and to the first capacitor;

a third transistor comprising a third control input and fifth and sixth current terminals, the fifth current terminal coupled to the second current terminal and the sixth current terminal coupled to a second power supply node;

a fourth transistor comprising a fourth control input and seventh and eighth current terminals, the fourth control input coupled to receive a second input control signal, the second input control signal being reciprocal to the first input control signal;

a second resistor coupled to the fourth control input of the fourth transistor;

a second capacitor coupled between the eighth current terminal of the fourth transistor and the second resistor; and

a fifth transistor comprising a fifth control input and ninth and tenth current terminals, the ninth current terminal coupled to the second resistor and to the second capacitor;

further comprising a latch, the latch including;

a pair of input transistors including control inputs coupled to the first and second resistors, respectively;

a pair of cross-coupled transistors coupled to one of the transistors of the pair of input transistors; and

a data pair of transistors including control inputs coupled to receive first and second data input signals to be held on output nodes of the latch responsive to voltages from the first and second resistors.

2. A circuit, comprising:

a first transistor comprising a first control input and first and second current terminals, the first control input coupled to receive a first input control signal, and the first current terminal coupled to a first power supply node;

a first resistor coupled to the first control input of the first transistor;

a first capacitor coupled between the second current terminal of the first transistor and the first resistor;

a second transistor comprising a second control input and third and fourth current terminals, the third current terminal coupled to the first resistor and to the first capacitor;

a third transistor comprising a third control input and seventh and eighth current terminals, the third control input coupled to receive a second input control signal, the second input control signal being reciprocal to the first input control signal; and

a second resistor coupled to the third control input;

a second capacitor coupled between the sixth current terminal and the second resistor; and

a fourth transistor comprising a fourth control input and seventh and eighth current terminals, the seventh current terminal coupled to the second resistor and to the second capacitor;

a first current source device coupled between the second current terminal and a second power supply node; and

a second current source device coupled between the sixth current terminal and the second power supply node.

3. The circuit of claim 2, wherein:

the second and fourth control inputs are coupled to receive a first common bias voltage; and

the first and second current source devices are biased with a second common bias voltage.

4. A circuit, comprising:

a first transistor comprising a first control input and first and second current terminals, the first control input coupled to receive a time-varying first input control signal;

a first resistor coupled to the first control input of the first transistor; and

a first high pass filter coupled to the second current terminal and to the first resistor at a first output node, the first high pass filter having a first cut-off frequency;

the voltage on the second current terminal of the first transistor provided through the first high pass filter to the first output node at frequencies of the time-varying first input control signal above the first cut-off frequency; and

at frequencies of the time-varying first input control signal below the first cut-off frequency, the voltage on the first output node being a voltage drop across the first resistor less than the time-varying first input control signal.

5. The circuit of claim 4, wherein the first high pass filter includes a capacitor connected to the second current terminal and to the first output node.

6. The circuit of claim 5, further comprising a second transistor coupled between the output node and a power supply node and biased to conduct a predetermined amount of current through the first resistor.

7. The circuit of claim 4, further comprising:

a second transistor comprising a second control input and third and fourth current terminals, the second control input coupled to receive a time-varying second input control signal reciprocal to the time-varying first input control signal;

a second resistor coupled to the second control input of the second transistor; and

a second high pass filter coupled to the fourth current terminal and to the second resistor at a second output node, the second high pass filter having a second cut-off frequency;

the voltage on the fourth current terminal of the second transmitter provided through the second high pass filter to the second output node at frequencies of the time-varying second input control signal above the second cut-off frequency; and

at frequencies of the time-varying second input control signal below the second cut-off frequency, the voltage on the second output node being a voltage drop across the second resistor less than the second input control signal.

8. The circuit of claim 7 further comprising a third transistor coupled between the second current terminal and a power supply node and a fourth transistor coupled between the fourth current terminal and the power supply node.

9. The circuit of claim 8, wherein the first and second transistors are bipolar junction transistors and the third and fourth transistors are metal oxide semiconductor field effect transistors.