Delay circuit
First Claim
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1. A delay circuit comprising:
- a variable delay line suitable for receiving an input signal and generating an output signal by delaying the input signal;
a first phase difference detector suitable for detecting a phase difference between the input signal and a first clock;
a second phase difference detector suitable for detecting a phase difference between the output signal and a second clock; and
a control circuit suitable for adjusting a delay value of the variable delay line in response to a detection result of the first phase difference detector and a detection result of the second phase difference detector,wherein the first and second clocks have a phase difference corresponding to a target delay value of the variable delay line, andeach of the first and second phase difference detectors comprises a time-to-digital converter.
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Abstract
A delay circuit includes: a variable delay line suitable for receiving an input signal and generating an output signal by delaying the input signal; a first phase difference detector suitable for detecting a phase difference between the input signal and a first clock; a second phase difference detector suitable for detecting a phase difference between the output signal and a second clock; and a control circuit suitable for adjusting a delay value of the variable delay line in response to a detection result of the first phase difference detector and a detection result of the second phase difference detector.
28 Citations
10 Claims
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1. A delay circuit comprising:
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a variable delay line suitable for receiving an input signal and generating an output signal by delaying the input signal; a first phase difference detector suitable for detecting a phase difference between the input signal and a first clock; a second phase difference detector suitable for detecting a phase difference between the output signal and a second clock; and a control circuit suitable for adjusting a delay value of the variable delay line in response to a detection result of the first phase difference detector and a detection result of the second phase difference detector, wherein the first and second clocks have a phase difference corresponding to a target delay value of the variable delay line, and each of the first and second phase difference detectors comprises a time-to-digital converter. - View Dependent Claims (2, 3, 4, 5)
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6. A memory system comprising:
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a memory device; and a memory controller including a delay circuit, wherein the delay circuit includes; a variable delay line suitable for receiving a data strobe signal as an input signal from the memory device and generating an output signal by delaying the input signal; a first phase difference detector suitable for detecting a phase difference between the input signal and a first clock; a second phase difference detector suitable for detecting a phase difference between the output signal and a second clock; and a control circuit suitable for adjusting a delay value of the variable delay line in response to a detection result of the first phase difference detector and a detection result of the second phase difference detector, wherein the first and second clocks have a phase difference corresponding to a target delay value of the variable delay line, and each of the first and second phase difference detectors comprises a time-to-digital converter. - View Dependent Claims (7, 8, 9, 10)
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Specification