Coarse adjustment cell array applied to digitally controlled oscillator and related apparatus
First Claim
1. A coarse adjustment cell array applied to a digitally controlled oscillator, the coarse adjustment cell array comprising:
- X coarse adjustment cells each comprising a logic cell and W fine adjustment cells; and
at least one logic cell of a coarse adjustment cell (i) is configured to receive Y coarse adjustment control bits and W fine adjustment control bits and control the W fine adjustment cells, wherein Y is an integer greater than 1, X is an integer greater than 1, and W is an integer greater than 1, wherein when the Y coarse adjustment control bits are a third value, the logic cell of the coarse adjustment cell (i) is configured to control, based on a value of the W fine adjustment control bits, some of the W fine adjustment cells in the coarse adjustment cell (i) to work.
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Accused Products
Abstract
The disclosure discloses a coarse adjustment cell array applied to a digitally controlled oscillator and a related apparatus. The coarse adjustment cell array applied to the digitally controlled oscillator includes X coarse adjustment cells, and each coarse adjustment cell in the coarse adjustment cell array includes a logic cell and W fine adjustment cells; and input to a logic cell of a coarse adjustment cell i in the coarse adjustment cell array includes Y coarse adjustment control bits and W fine adjustment control bits, output from the logic cell of the coarse adjustment cell i is used to control whether W fine adjustment cells in the coarse adjustment cell i work, Y is an integer greater than 1, and X and W are integers greater than 1.
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Citations
12 Claims
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1. A coarse adjustment cell array applied to a digitally controlled oscillator, the coarse adjustment cell array comprising:
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X coarse adjustment cells each comprising a logic cell and W fine adjustment cells; and at least one logic cell of a coarse adjustment cell (i) is configured to receive Y coarse adjustment control bits and W fine adjustment control bits and control the W fine adjustment cells, wherein Y is an integer greater than 1, X is an integer greater than 1, and W is an integer greater than 1, wherein when the Y coarse adjustment control bits are a third value, the logic cell of the coarse adjustment cell (i) is configured to control, based on a value of the W fine adjustment control bits, some of the W fine adjustment cells in the coarse adjustment cell (i) to work. - View Dependent Claims (2, 3, 4, 5)
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6. A digitally controlled oscillator, comprising:
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a coarse adjustment cell array, comprising; X coarse adjustment cells each comprising a logic cell and W fine adjustment cells, and at least one logic cell of a coarse adjustment cell (i) is configured to receive Y coarse adjustment control bits and W fine adjustment control bits and control the W fine adjustment cells, wherein Y is an integer greater than 1, X is an integer greater than 1, and W is an integer greater than 1; a coarse adjustment row-column decoder configured to decode an input first control signal and output A coarse adjustment control bits; a fine adjustment row-column decoder configured to decode an input second control signal and output B fine adjustment control bits; and wherein a set formed by the Y coarse adjustment control bits is a subset of a set comprising the A coarse adjustment control bits, and a set comprising the W fine adjustment control bits is a subset of a set comprising the B fine adjustment control bits. - View Dependent Claims (7, 8, 9, 10)
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11. A frequency synthesizer, comprising:
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a digitally controlled oscillator, comprising; a coarse adjustment cell array, comprising; X coarse adjustment cells each comprising a logic cell and W fine adjustment cells; and at least one logic cell of a coarse adjustment cell (i) is configured to receive Y coarse adjustment control bits and W fine adjustment control bits and control the W fine adjustment cells, wherein Y is an integer greater than 1, X is an integer greater than 1, and W is an integer greater than 1, a coarse adjustment row-column decoder configured to decode a first control signal and output A coarse adjustment control bits, a fine adjustment row-column decoder configured to decode a second control signal and output B fine adjustment control bits, and wherein a set formed by the Y coarse adjustment control bits is a subset of a set comprising the A coarse adjustment control bits, and a set comprising the W fine adjustment control bits is a subset of a set comprising the B fine adjustment control bits; and a digital logic cell configured to output the first control signal to the coarse adjustment row-column decoder and output the second control signal to the fine adjustment row-column decoder. - View Dependent Claims (12)
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Specification