Serializer and semiconductor system including the same
First Claim
1. A serializer, comprising:
- a data trigger circuit suitable for latching a plurality of input data based on a plurality of clocks having a predetermined phase difference to output a plurality of aligned data and a plurality of complementary aligned data;
a hybrid multiplexing circuit suitable for outputting a pull-down signal and a pull-up signal that are selectively controlled based on a pull-down control signal which is generated by removing an input loading of the aligned data and a pull-up control signal which is generated by removing an input loading of the complementary aligned data; and
an output driver suitable for outputting serial data corresponding to the pull-up signal and the pull-down signal.
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Abstract
A serializer includes: a data trigger circuit suitable for latching a plurality of input data based on a plurality of clocks having a predetermined phase difference to output a plurality of aligned data and a plurality of complementary aligned data; a hybrid multiplexing circuit suitable for outputting a pull-down signal and a pull-up signal that are selectively controlled based on a pull-down control signal which is generated by removing an input loading of the aligned data and a pull-up control signal which is generated by removing an input loading of the complementary aligned data; and an output driver suitable for outputting serial data corresponding to the pull-up signal and the pull-down signal.
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Citations
20 Claims
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1. A serializer, comprising:
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a data trigger circuit suitable for latching a plurality of input data based on a plurality of clocks having a predetermined phase difference to output a plurality of aligned data and a plurality of complementary aligned data; a hybrid multiplexing circuit suitable for outputting a pull-down signal and a pull-up signal that are selectively controlled based on a pull-down control signal which is generated by removing an input loading of the aligned data and a pull-up control signal which is generated by removing an input loading of the complementary aligned data; and an output driver suitable for outputting serial data corresponding to the pull-up signal and the pull-down signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor system, comprising:
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a first semiconductor device; and a second semiconductor device suitable for serially communicating with the first semiconductor device through a transfer line, wherein each of the first semiconductor device and the second semiconductor device includes the transfer line for converting parallel internal data into a serial data, and the transfer line includes; a data trigger circuit suitable for latching an internal data based on a plurality of clocks having a predetermined phase difference to output a plurality of aligned data and a plurality of complementary aligned data; a hybrid multiplexing circuit suitable for outputting a pull-down signal and a pull-up signal that are selectively driven based on a pull-down control signal which is generated by removing an input loading of the aligned data and a pull-up control signal which is generated by removing an input loading of the complementary aligned data; and an output driver suitable for outputting the serial data corresponding to the pull-up signal and the pull-down signal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification