Memory decision feedback equalizer bias level generation

• US 10,644,909 B2
• Filed: 05/29/2019
• Issued: 05/05/2020
• Est. Priority Date: 01/08/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sreeramaneni, Raghukiran, Taylor, Jennifer E.
• Primary Examiner(s): Corrielus, Jean B
• Application Number:
  US16/425,653
• Publication Number:
  US 20190280907A1
• Time in Patent Office: 342 Days
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04L 25/021 Estimation of channel covariance
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

A device includes a selection circuit that is configured to generate a bias level. The device also includes a combinational circuit coupled to the selection circuit. The combinational circuit is configured to generate a distortion correction factor used offset inter-symbol interference from a data stream on a distorted bit based on the bias level to generate a correction signal. The device additionally includes a latching element coupled to the combinational circuit and configured to receive the first correction signal.

Claims

1. A device, comprising:

a selection circuit configured to generate a bias level, wherein the selection circuit comprises a receiver coupled to an operational amplifier, wherein the operational amplifier is configured to transmit an output to an input of the receiver to adjust the bias level;

a combinational circuit coupled to the selection circuit and configured to generate a distortion correction factor used to offset inter-symbol interference from a data stream on a distorted bit based on the bias level to generate a correction signal; and

a data latch coupled to the combinational circuit and configured to receive the correction signal to generate a corrected bit.

2. The device of claim 1, wherein the selection circuit is configured to adjust the bias level in response to operating conditions affecting the combinational circuit.

3. The device of claim 1, wherein the combinational circuit comprises a summer circuit.

4. The device of claim 3, wherein the summer circuit is configured to utilize a weighted tap value to apply a current to generate at least a portion of the distortion correction factor.

5. The device of claim 4, wherein the summer circuit comprises a controllable source configured to supply the current.

6. The device of claim 5, wherein the controllable source comprises a current source controlled by the bias level to generate the current.

7. The device of claim 4, wherein the summer circuit is configured to utilize a second weighted tap value to apply a second current to generate at least a second portion of the distortion correction factor.

8. The device of claim 7, wherein the summer circuit comprises a second controllable source configured to supply the second current.

9. The device of claim 8, wherein the second controllable source comprises a current source controlled by a second bias level to generate the second current.

10. The device of claim 9, wherein the selection circuit is configured to generate the second bias level, wherein the combinational circuit is configured to generate the distortion correction factor used to offset inter-symbol interference from the data stream on the distorted bit additionally based on the second bias level to generate the correction signal.

11. The device of claim 1, wherein the operational amplifier is configured to generate the output based upon a difference between a first signal received from the receiver and second signal received from the receiver.

12. A device, comprising:

an equalizer, comprising;

a first input configured to receive distorted input data as part of a data stream; and

a summer circuit configured to apply a correction factor to the distorted input data to offset inter-symbol interference from the data stream on the distorted input data, wherein the summer circuit comprises a controllable source configured to supply a current, wherein the controllable source comprises a current source controlled by a bias level to generate the current, wherein the summer circuit is configured to receive and utilize a first weighted tap value to apply the current to the distorted input data as at least a portion of the correction factor.

13. The device of claim 12, wherein the summer circuit is configured to apply the current to the distorted input data to offset inter-symbol interference from a data bit of the data stream received just prior to the distorted input data.

14. The device of claim 13, wherein the summer circuit comprises a second controllable source configured to supply a second current, wherein the second controllable source comprises a second current source controlled by a second bias level to generate the second current, wherein the summer circuit is configured to receive and utilize a second weighted tap value to apply the second current to the distorted input data as at least a second portion of the correction factor.

15. The device of claim 14, wherein the summer circuit is configured to apply the current to the distorted input data to offset inter-symbol interference from a second data bit of the data stream received just prior to the data bit.

16. The device of claim 12, wherein the bias level is generated in response to a change in process, voltage, or temperature changes affecting operation of equalizer.

17. A device, comprising:

an equalizer, comprising;

a first input configured to receive distorted input data as part of a data stream;

a second input configured to receive a reference signal; and

a summer circuit, comprising;

a first controllable source configured to supply a first current, wherein the first controllable source comprises a first current source controlled by a first bias level to generate the first current, wherein the summer circuit is configured to receive and utilize a first weighted tap value to apply the first current to the distorted input data to generate modified input data; and

a second controllable source configured to supply a second current, wherein the second controllable source comprises a second current source controlled by a second bias level to generate the second current, wherein the summer circuit is configured to receive and utilize a second weighted tap value to apply the second current to the reference signal to generate a modified reference signal, wherein the first weighted tap value and the second weighted tap value are selected to offset inter-symbol interference from the data stream on the distorted input data.

18. The device of claim 17, wherein the equalizer comprises a data latch coupled to the summer circuit, wherein the data latch is configured to transmit a corrected data bit generated based upon the modified input data and the modified reference signal.

19. The device of claim 17, wherein the first bias level is generated in response to operating conditions affecting the equalizer.

20. The device of claim 17, wherein the first controllable source is configured to supply the first current having an equal value to the second current supplied by the second controllable source.

21. The device of claim 17, wherein the first current source is controlled by the first bias level having an equal value to the second bias level controlling the second current source.