Reverse order queue updates by virtual devices

• US 10,649,784 B2
• Filed: 05/29/2018
• Issued: 05/12/2020
• Est. Priority Date: 05/29/2018
• Status: Active Grant

• Current Assignee: Red Hat, Inc. (International Business Machines Corporation)
• Original Assignee: Red Hat, Inc. (International Business Machines Corporation)
• Inventors: Tsirkin, Michael
• Primary Examiner(s): Bragdon, Reginald G
• Assistant Examiner(s): Vo, Thanh D
• Application Number:
  US15/991,490
• Publication Number:
  US 20190370002A1
• Time in Patent Office: 714 Days
• CPC Class Codes: G06F 12/0851 Cache with interleaved addressing
• CPC Class Codes: G06F 12/0857 by multiple requestors
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/152 Virtualized environment, e.g. logically partitioned system
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/45545 Guest-host, i.e. hypervisor is an application program itself, e.g. VirtualBox
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

A system includes a memory including a ring buffer having a plurality of slots, a processor in communication with the memory, a guest operating system, and a hypervisor. The hypervisor is configured to detect a request associated with a memory entry, retrieve up to a predetermined quantity of memory entries in the ring buffer from an original slot to an end slot, and test a respective descriptor of each successive slot from the original slot through the end slot while the respective descriptor of each successive slot in the ring buffer remains unchanged. Additionally, the hypervisor is configured to execute the request associated with the memory entries and respective valid descriptors. The hypervisor is also configured to walk the ring buffer backwards from the end slot to the original slot while clearing the valid descriptors.

Claims

1. A system comprising:

a memory including a ring buffer having a plurality of slots;

a processor in communication with the memory;

a guest operating system; and

a hypervisor, wherein the hypervisor is configured to;

detect a request associated with a memory entry,

retrieve up to a predetermined quantity of memory entries in the ring buffer from an original slot to an end slot,

test a respective descriptor of each successive slot from the original slot through the end slot while the respective descriptor of each successive slot in the ring buffer remains unchanged,

responsive to determining the respective descriptor is a valid descriptor, execute the request associated with the memory entry and the respective descriptor,

walk the ring buffer backwards from the end slot to the original slot, and

clear the valid descriptor in each slot between the end slot and the original slot.

2. The system of claim 1, wherein the request is one of (i) a request to transmit the respective memory entry from the memory, (ii) a request to copy the respective memory entry into a virtual machine memory, or (iii) a request to copy the respective memory entry out of a virtual machine memory.

3. The system of claim 1, wherein the hypervisor is configured to detect the request from the guest operating system.

4. The system of claim 1, wherein the predetermined quantity of memory entries includes a first memory entry in the original slot, a second memory entry in an intermediate slot, and a third memory entry located in the end slot.

5. The system of claim 1, wherein the descriptor is at least one of a bit, a field entry, an address, and a packet length, and wherein a valid descriptor is at least one of a valid bit, a special value in the field entry, a non-zero address, and a non-zero packet length.

6. A method comprising:

detecting, by a hypervisor, a request to associated with a memory entry;

retrieving, by the hypervisor, up to a predetermined quantity of memory entries in the ring buffer from an original slot to an end slot;

testing, by the hypervisor, a respective descriptor of each successive slot from the original slot through the end slot while the respective descriptor of each successive slot in the ring buffer remains unchanged;

responsive to determining the respective descriptor is a valid descriptor, executing, by the hypervisor, the request associated with the memory entry and the respective descriptor;

walking, by the hypervisor, the ring buffer backwards from the end slot to the original slot; and

clearing, by the hypervisor, the valid descriptor in each slot between the end slot and the original slot.

7. The method of claim 6, wherein the request is one of (i) a request to transmit the respective memory entry from a first memory to a second memory, (ii) a request to copy the respective memory entry into a virtual machine memory, or (iii) a request to copy the respective memory entry out of a virtual machine memory.

8. The method of claim 6, wherein the predetermined quantity of memory entries are stored in a first quantity of slots, the hypervisor retrieves a second quantity of memory entries, and the second quantity is less than the first quantity.

9. The method of claim 8, further comprising copying packet data into the VM memory from the retrieved packet addresses.

10. The method of claim 6, wherein walking the ring buffer backwards includes counting the quantity of memory entries as they are retrieved.

11. The method of claim 6, wherein walking the ring buffer backwards includes decrementing a counter while walking the ring buffer backwards.

12. The method of claim 6, wherein clearing the valid descriptor in each slot includes overwriting the descriptor with a different value.

13. The method of claim 6, wherein the hypervisor detects the request from a guest operating system.

14. The method of claim 6, wherein the predetermined quantity of memory entries includes a first memory entry in the original slot, a second memory entry in an intermediate slot, and a third memory entry located in the end slot.

15. The method of claim 6, wherein the hypervisor stops testing responsive to receiving a value other than a valid descriptor from one of the successive slots from the original slot through the end slot.

16. The method of claim 6, wherein the hypervisor stops testing responsive to retrieving the predetermined quantity of memory entries in the ring buffer.

17. The method of claim 6, wherein a cache line bounce occurs after clearing the valid descriptor in the original slot.

18. The method of claim 6, wherein clearing the valid descriptor includes one of overwriting a valid bit with an invalid bit, deleting a special entry in a valid field, overwriting a packet address with a zero value or NULL value, and changing a packet length to an invalid packet length.

19. A method comprising:

receiving, by a hypervisor, a request associated with a memory entry;

storing, by the hypervisor, a location of an original slot in hypervisor memory;

testing, by the hypervisor, a respective descriptor of each successive slot from the original slot through an end slot while the respective descriptor of each successive slot in the ring buffer remains unchanged;

responsive to determining the respective descriptor is a valid descriptor, executing, by the hypervisor, the request associated with the memory entry and the respective descriptor;

responsive to executing the requests associated with each of the respective descriptors in the original slot through the end slot, incrementing, by the hypervisor, a counter from an original value to an end value; and

clearing, by the hypervisor, the valid descriptor in each slot between the end slot and the original slot while walking the ring buffer backwards.

20. The method of claim 19, wherein the hypervisor stops testing (i) responsive to receiving a value other than a valid descriptor from one of the successive slots from the original slot through the end slot or (ii) responsive to retrieving the predetermined quantity of memory entries in the ring buffer.