Block management for dynamic single-level cell buffers in storage devices

• US 10,650,886 B2
• Filed: 02/28/2019
• Issued: 05/12/2020
• Est. Priority Date: 12/22/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Natarajan, Shankar, Natarajan, Sriram, Nagarajan, Suresh, Ganesan, Ramkarthik, Athreya, Arun S., Trivedi, Romesh B.
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): Radke, Jay W.
• Application Number:
  US16/288,268
• Publication Number:
  US 20190267080A1
• Time in Patent Office: 439 Days
• Field of Search: 711170
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.

Claims

1. A semiconductor apparatus comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to;

determine a programmable eviction ratio associated with a storage device,

convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio,

wherein when the storage device is in a runtime state, the programmable eviction ratio is to be retrieved from a data structure dedicated to the runtime state, and wherein when the storage device is in an idle state, the programmable eviction ratio is to be retrieved from a data structure dedicated to the idle state.

2. The semiconductor apparatus of claim 1, wherein when the storage device is in the idle state, the portion converted into the multi-level cell region is to be from a static single-level cell region.

3. The semiconductor apparatus of claim 1, wherein when the storage device is in the runtime state, the portion converted into the multi-level cell region is to be from a dynamic single-level cell region.

4. The semiconductor apparatus of claim 1, wherein when the storage device is in the runtime state, the logic coupled to the one or more substrates is to:

determine whether a threshold of a static single-level cell region is reached; and

when the threshold is not reached, conduct a write operation on a memory block in the static single-level cell region.

5. The semiconductor apparatus of claim 4, wherein the logic coupled to the one or more substrates is to:

when the threshold is reached, determine whether a threshold of a dynamic single-level cell region is reached; and

when the threshold of the dynamic single-level cell region is not reached, conduct a write operation on a memory block in the dynamic single-level cell region.

6. The semiconductor apparatus of claim 5, wherein the logic coupled to the one or more substrates is to:

when the threshold of the dynamic single-level cell region is reached, retrieve the programmable eviction ratio; and

convert a portion of the dynamic single-level cell region into the multi-level cell region in accordance with the programmable eviction ratio.

7. A storage device comprising:

a power supply to provide power to the storage device;

a memory array including a single-level cell region and a multi-level cell region;

a memory controller including logic to;

determine a programmable eviction ratio associated with the storage device, and

convert a portion of the single-level cell region into the multi-level cell region in accordance with the programmable eviction ratio,

wherein when the storage device is in a runtime state, the programmable eviction ratio is to be retrieved from a data structure dedicated to the runtime state, and wherein when the storage device is in an idle state, the programmable eviction ratio is to be retrieved from a data structure dedicated to the idle state.

8. The storage device of claim 7, wherein when the storage device is in the idle state, the portion converted into the multi-level cell region is to be from a static single-level cell region.

9. The storage device of claim 7, wherein when the storage device is in the runtime state, the portion converted into the multi-level cell region is to be from a dynamic single-level cell region.

10. The storage device of claim 7, wherein when the storage device is in the runtime state, the memory controller is to:

determine whether a threshold of a static single-level cell region is reached; and

when the threshold is not reached, conduct a write operation on a memory block in the static single-level cell region.

11. The storage device of claim 10, wherein the memory controller is to:

when the threshold is reached, determine whether a threshold of a dynamic single-level cell region is reached; and

when the threshold of the dynamic single-level cell region is not reached, conduct a write operation on a memory block in the dynamic single-level cell region.

12. The storage device of claim 11, wherein the memory controller is to:

when the threshold of the dynamic single-level cell region is reached, retrieve the programmable eviction ratio; and

convert a portion of the dynamic single-level cell region into the multi-level cell region in accordance with the programmable eviction ratio.

13. A method comprising:

determining a programmable eviction ratio associated with a storage device; and

converting a portion of a single-level cell region in the storage device into a multi-level cell region in the storage device in accordance with the programmable eviction ratio,

wherein when the storage device is in a runtime state, the programmable eviction ratio is retrieved from a data structure dedicated to the runtime state, and wherein when the storage device is in an idle state, the programmable eviction ratio is retrieved from a data structure dedicated to the idle state.

14. The method of claim 13, wherein when the storage device is in the idle state, the portion converted into the multi-level cell region is to be from a static single-level cell region.

15. The method of claim 13, wherein when the storage device is in the runtime state, the portion converted into the multi-level cell region is to be from a dynamic single-level cell region.

16. The method of claim 13, wherein the method further comprises when the storage device is in the runtime state:

determining whether a threshold of a static single-level cell region is reached; and

when the threshold is not reached, conducting a write operation on a memory block in the static single-level cell region.

17. The method of claim 16, wherein the method further comprises:

when the threshold is reached, determining whether a threshold of a dynamic single-level cell region is reached; and

when the threshold of the dynamic single-level cell region is not reached, conducting a write operation on a memory block in the dynamic single-level cell region.

18. The method of claim 17, wherein the method further comprises:

when the threshold of the dynamic single-level cell region is reached, retrieving the programmable eviction ratio; and

converting a portion of the dynamic single-level cell region into the multi-level cell region in accordance with the programmable eviction ratio.