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Block management for dynamic single-level cell buffers in storage devices

  • US 10,650,886 B2
  • Filed: 02/28/2019
  • Issued: 05/12/2020
  • Est. Priority Date: 12/22/2017
  • Status: Active Grant
First Claim
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1. A semiconductor apparatus comprising:

  • one or more substrates; and

    logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to;

    determine a programmable eviction ratio associated with a storage device,convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio,wherein when the storage device is in a runtime state, the programmable eviction ratio is to be retrieved from a data structure dedicated to the runtime state, and wherein when the storage device is in an idle state, the programmable eviction ratio is to be retrieved from a data structure dedicated to the idle state.

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