Memory devices with distributed block select for a vertical string driver tile architecture
First Claim
1. A memory device having a tile architecture, the memory device comprising:
- a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry, at least one portion of the distributed block select circuit within a first pair of tiles of the multiple pairs of tiles physically offset, in a first direction, from at least one other portion of the distributed block select circuit within a second pair of tiles of the multiple pairs of tiles, each pair of tiles of the multiple pair of tiles having an associated vertical string driver physically offset, in a second, different direction, from each of a first tile and a second tile of an associated pair of tiles.
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Accused Products
Abstract
Memory device having a tile architecture are disclosed. The memory device may include a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry. Another memory device may include a memory array, and a CMOS under array region. At least some tile regions may include portions of a total amount of block select circuitry distributed throughout the CUA region, vertical string drivers located outside of the memory array, and page buffer circuitry coupled with the memory array. Another memory device may include a first tile pair including a first tile, a second tile, a first vertical string driver therebetween, a first page buffer region that is greater than 50% of area for the first tile pair, and a first portion of a distributed block select circuitry.
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Citations
20 Claims
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1. A memory device having a tile architecture, the memory device comprising:
a first plane having multiple pairs of tiles, wherein at least some of the pairs of tiles of the first plane include a distributed block select circuit and page buffer circuitry, at least one portion of the distributed block select circuit within a first pair of tiles of the multiple pairs of tiles physically offset, in a first direction, from at least one other portion of the distributed block select circuit within a second pair of tiles of the multiple pairs of tiles, each pair of tiles of the multiple pair of tiles having an associated vertical string driver physically offset, in a second, different direction, from each of a first tile and a second tile of an associated pair of tiles. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory device, comprising:
a number of pairs of tiles, each pair of tiles of the number of pairs of tiles including a first tile and a second tile, each of the first tile and the second tile including; a portion of a distributed block select circuit for the number of pairs of tiles; additional circuity; and a page buffer having an area greater than a combined area of the portion of the distributed block select circuit and the additional circuitry of the associated tile. - View Dependent Claims (11, 12, 13, 14)
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15. A memory device, comprising:
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a first tile pair including a first tile, a second tile, and a first vertical string driver offset from the first tile and the second tile in a first direction, the first tile including a first portion of a distributed block select circuitry and the second tile including a second portion of the distributed block select circuitry; and a second tile pair including a third tile, a fourth tile, and a second vertical string driver offset from the third tile and the fourth tile in the first direction, the third tile including a third portion of the distributed block select circuitry and the fourth tile including a fourth portion of the distributed block select circuitry; wherein each of the first portion of the distributed block select circuity, the second portion of the distributed block select circuity, the third portion of the distributed block select circuity, and the fourth portion of the distributed block select circuity are offset from every other portion of the distributed block select circuitry in a second, different direction. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification