Non-volatile memory devices, operating methods thereof and memory systems including the same

• US 10,650,903 B2
• Filed: 11/30/2018
• Issued: 05/12/2020
• Est. Priority Date: 02/17/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shim, Sun-Il, Jang, Jae-Hoon, Chae, Donghyuk, Lim, Youngho, Kim, Hansoo, Jeong, Jaehun
• Primary Examiner(s): Mai, Son L
• Application Number:
  US16/206,383
• Publication Number:
  US 20190096495A1
• Time in Patent Office: 529 Days
• Field of Search: 36518528, 36518518
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Claims

1. A method of programming a nonvolatile memory device including a plurality of memory cells stacked on a substrate in a direction vertical to the substrate, each of the plurality of memory cells coupled to corresponding word line among a plurality of word lines stacked along the plurality of memory cells, and the plurality of memory cells being divided into a first portion and a second portion, the second portion being stacked over the first portion, the method comprising:

applying a first program voltage on a first word line located in the first portion;

applying a first pass voltage on a third word line located in the first portion while applying the first program voltage on the first word line;

applying a second program voltage on a second word line located in the first portion; and

applying a second pass voltage on the first word line located in the first portion while applying the second program voltage on the second word line,

wherein the second word line is located farther from the substrate than the first word line and adjacent to the first word line, the third word line is located farther from the substrate than the second word line and adjacent to the second word line, and a level of the first pass voltage is higher than a level of the second pass voltage.

2. The method of claim 1, wherein the method further comprising:

applying a third pass voltage on a fourth word line while applying the first program voltage on the first word line and while applying the second program voltage to the second word line, the fourth word line being located in the first portion farthest from the substrate among the plurality of word lines; and

applying a fourth pass voltage on a fifth word line while applying the first and second program voltages on the first and second word lines respectively, the fifth word line being located in the second portion and farthest from the substrate among the plurality of word lines.

3. The method of claim 2, wherein the first portion and the second portion are formed through separate etching process steps respectively.

4. The method of claim 3, wherein the method further comprising:

applying a first read voltage on the first word line after applying the first program voltage on the first word line;

applying a fourth pass voltage on the second word line;

applying a second read voltage on the second word line after applying the second program voltage on the second word line; and

applying a fifth pass voltage on the third word line,

wherein the level of the fifth pass voltage is higher than the level of the fourth pass voltage.

5. The method of claim 4, wherein the method further comprising:

applying a sixth pass voltage on the fourth word line while applying the first read voltage on the first word line and while applying the second read voltage to the second word line; and

applying a seventh pass voltage on the fifth word line while applying the first read voltage on the first word line and while applying the second read voltage to the second word line.

6. The method of claim 1, wherein the method further comprising:

applying a third program voltage on the first word line after applying the first program voltage;

applying a fifth pass voltage on the third word line while applying the third program voltage on the first word line;

applying a fourth program voltage on the second word line after applying the second program voltage; and

applying a sixth pass voltage on the first word line while applying the fourth program voltage on the second word line,

wherein the third program voltage is higher than the first program voltage by a first increment, and the fourth program voltage is higher than the second program voltage by a second increment, and the second increment is greater than the first increment.

7. The method of claim 1, wherein the method further includes applying three different pass voltages on three word lines located in the first portion and closest to the substrate respectively, each of the three different pass voltages being greater as a distance between the word line and the substrate increases.

8. The method of claim 1, wherein the method further includes applying three different pass voltages on three word lines located in the second portion and farthest from the substrate respectively, each of the three different pass voltages being greater as a distance between the word line and the substrate increases.

9. A method of programming a nonvolatile memory device including a plurality of memory cells stacked on a substrate in a direction vertical to the substrate, each of the plurality of memory cells coupled to corresponding word line among a plurality of word lines stacked along the plurality of memory cells, and the plurality of memory cells being divided into a first portion and a second portion, the second portion being stacked over the first portion, the method comprising:

applying a first program voltage on a first word line located in the first portion; and

applying a first pass voltage on a second word line and applying a second pass voltage on a third word line respectively, the second word line being located farther from the substrate than the first word line and adjacent to the first word line, the third word line being located farther from the substrate than the second word line and adjacent to the second word line,

wherein a level of the second pass voltage is greater than a level of the first pass voltage.

10. The method of claim 9, wherein the method further comprising:

applying a third pass voltage on a fourth word line while applying the first program voltage on the first word line, the fourth word line being located in the first portion and farthest from the substrate among the plurality of word lines; and

applying a fourth pass voltage on a fifth word line while applying the first program voltage on the first word line, the fifth word line being located in the second portion and farthest from the substrate among the plurality of word lines.

11. The method of claim 10, wherein the first portion and the second portion are formed through separate etching process steps respectively.

12. The method of claim 11, wherein the method further comprising:

applying a first read voltage on the first word line after applying the first program voltage on the first word line; and

applying a fifth pass voltage on the second word line and applying a sixth pass voltage on the third word line respectively while applying the first verify voltage on the first word line,

wherein the level of the sixth pass voltage is higher than the level of the fifth pass voltage.

13. The method of claim 12, wherein the method further comprising:

applying a seventh pass voltage on the fourth word line while applying the first read voltage on the first word line; and

applying a eighth pass voltage on the fifth word line while applying the first read voltage on the first word line.

14. The method of claim 9, wherein the method further comprising:

applying a second program voltage on the first word line after applying the first program voltage on the first word line;

applying a third program voltage on the second word line;

applying a fourth program voltage on the second word line after applying the third program voltage on the second word line;

applying a fifth pass voltage on the second word line while applying the second program voltage on the first word line; and

applying a sixth pass voltage on the third word line while applying the second program voltage on the first word line,

wherein the second program voltage is higher than the first program voltage by a first increment, and the fourth pass voltage is higher than the third program voltage by a second increment, and the first increment is smaller than the second increment.

15. The method of claim 9, wherein the method further includes applying three different pass voltages on three word lines located in the first portion and closest to the substrate respectively, each of the three different pass voltages being greater as a distance between the word line and the substrate increases.

16. The method of claim 9, wherein the method further includes applying three different pass voltages on three word lines located in the second portion and farthest from the substrate respectively, each of the three different pass voltages being greater as a distance between the word line and the substrate increases.