3D semiconductor device and structure

• US 10,651,054 B2
• Filed: 08/28/2018
• Issued: 05/12/2020
• Est. Priority Date: 12/29/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian, Sekar, Deepak
• Primary Examiner(s): Page, Dale E
• Assistant Examiner(s): Baptiste, Wilner Jean
• Application Number:
  US16/115,519
• Publication Number:
  US 20190019693A1
• Time in Patent Office: 623 Days
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 23/3732 Diamonds
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0248 : for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/098 : the components being PN junction gate field-effect transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes a Phase Lock Loop (“PLL”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.

Claims

1. A 3D semiconductor device, the device comprising:

a first level comprising;

(i) a first single crystal layer,

wherein said first single crystal layer includes a plurality of first transistors and (ii) a first metal layer,

wherein said first metal layer comprises interconnections between said first transistors, and

wherein at least a portion of said first transistors form a plurality of logic gates;

a second level comprising a plurality of second transistors,

wherein said second transistors are atop said first metal layer;

a second metal layer overlaying, at least in part said second transistors;

Input/Output pad structures to provide connections to external devices;

a global power grid configured to distribute power to said device,

wherein at least part of said global power grid is disposed above said second metal layer; and

a local power grid configured to distribute power to said plurality of logic gates,

wherein said second transistors are aligned to said first transistors with less than 40 nm misalignment,

wherein said first single crystal layer comprises an electrostatic discharge (“

ESD”

) structure connected to at least one of said Input/Output pad structures,

wherein said local power grid is disposed underneath said second level,

wherein said global power grid is connected to said local power grid by a plurality of vias,

wherein said global power grid includes a first conductor comprising a first current carrying capacity and said local power grid includes a second conductor comprising a second current carrying capacity,

wherein said first current carrying capacity is at least twice said second current carrying capacity,

wherein at least one of said plurality of vias has a radius of less than 200 nm,

wherein at least one of said second transistors comprises a source, a drain, and a transistor channel,

wherein said source, said drain and said transistor channel comprise a same dopant type,

wherein a memory cell comprises at least one of said second transistors, and

wherein said memory cell is at least partially atop at least one of said logic gates.

2. The 3D semiconductor device according to claim 1,

wherein at least a portion of said plurality of vias are configured to remove heat from said second level.

3. The 3D semiconductor device according to claim 1, further comprising:

a connective path from said second transistors to said first transistors,

wherein said path comprises a through-layer via, and

wherein said through-layer via comprises tungsten.

4. The 3D semiconductor device according to claim 1,

wherein said second transistors comprise polysilicon.

5. The 3D semiconductor device according to claim 1, further comprising:

a first guard ring; and

a second guard ring,

wherein said first guard ring surrounds said plurality of first transistors and said second guard ring surrounds said plurality of second transistors.

6. The 3D semiconductor device according to claim 1,

wherein at least one of said second transistors at least partially overlays at least one of said first transistors.

7. A 3D semiconductor device, the device comprising:

a first level comprising;

(i) a first single crystal layer

wherein said first single crystal layer includes a plurality of first transistors and (ii) a first metal layer,

wherein said first metal layer comprises interconnections between said first transistors, and

wherein at least a portion of said first transistors form a plurality of logic gates;

a second level comprising a plurality of second transistors,

wherein said second transistors are atop said first metal layer;

a second metal layer overlaying, at least in part said second transistors; and

Input/Output pad structures to provide connections to external devices,

wherein said second transistors are aligned to said first transistors with less than 40 nm misalignment,

wherein said first single crystal layer comprises an electrostatic discharge (“

ESD”

) structure connected to at least one of said Input/Output pad structures,

wherein at least one of said second transistors comprises a source, a drain, and a transistor channel,

wherein said source, said drain and said transistor channel comprise a same dopant type,

wherein a memory cell comprises at least one of said second transistors,

wherein said local power grid is disposed underneath said second level,

wherein said global power grid is connected to said local power grid by a plurality of vias.

8. The 3D semiconductor device according to claim 7,

wherein at least one of said vias has a radius of less than 200 nm.

9. The 3D semiconductor device according to claim 7, further comprising:

further comprising;

a connective path from said second transistors to said first transistors,

wherein said path comprises a through-layer via, and

wherein said through-layer via comprises tungsten.

10. The 3D semiconductor device according to claim 7,

wherein said second transistors comprise polysilicon.

11. The 3D semiconductor device according to claim 7, further comprising:

a Phase Lock Loop (“

PLL”

) structure connected to at least one of said input/output pad structures.

12. The 3D semiconductor device according to claim 7,

wherein at least one of said second transistors at least partially overlays at least one of said first transistors.

13. The 3D semiconductor device according to claim 7, further comprising:

a connective path from said second transistors to said first transistors,

wherein said path comprises a through-layer via,

wherein said through-layer via contacts to said second transistor source or drain.

14. The 3D semiconductor device according to claim 7,

wherein at least a portion of said plurality of vias are configured to remove heat from said second level.

15. A 3D semiconductor device, the device comprising:

a first level comprising;

(i) a first single crystal layer,

wherein said first single crystal layer includes a plurality of first transistors and iii) a first metal layer,

wherein said first metal layer comprises interconnections between said first transistors, and

wherein at least a portion of said first transistors form a plurality of logic gates;

a second level comprising a plurality of second transistors,

wherein said second transistors are atop said first metal layer;

a second metal layer overlaying, at least in part said second transistors; and

Input/Output pad structures to provide connections to external devices,

wherein said second transistors are aligned with less than 40 nm misalignment to said first transistors, and

wherein said first single crystal layer comprises an electrostatic discharge (“

ESD”

) structure connected to at least one of said Input/Output pad structures,

wherein at least one of said second transistors comprises a source, a drain, and a transistor channel,

wherein said source, said drain and said transistor channel comprise a same dopant type, and

wherein said second metal layer has a current carrying capacity at least twice a current carrying capacity than said first metal layer.

16. The 3D semiconductor device according to claim 15,

wherein said third transistors comprise polysilicon.

17. The 3D semiconductor device according to claim 15, further comprising:

a connective path from said second transistors to said first transistors,

wherein said path comprises a through-layer via,

wherein said through-layer via contacts to said second transistor source or drain.

18. The 3D semiconductor device according to claim 15, further comprising:

a plurality of vias connecting said second metal layer to said first metal layer,

wherein at least one of said plurality of vias comprises tungsten.

19. The 3D semiconductor device according to claim 15, further comprising:

a Phase Lock Loop (“

PLL”

) structure connected to at least one of said Input/Output pad structures.

20. The 3D semiconductor device according to claim 15,

wherein at least one of said plurality of vias has a radius of less than 200 nm.