Apparatus and method of three dimensional conductive lines

• US 10,651,114 B2
• Filed: 12/18/2018
• Issued: 05/12/2020
• Est. Priority Date: 11/12/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chih-Yu, Lin, Kao-Cheng, Wang, Li-Wen, Chen, Yen-Huei
• Primary Examiner(s): Sefer, Ahmed N
• Application Number:
  US16/224,159
• Publication Number:
  US 20190122960A1
• Time in Patent Office: 511 Days
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/10 including a plurality of individual components in a repetitive configuration
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

Claims

1. An inter-tier memory column, comprising:

a first bit line, comprising;

a first segment disposed within a first tier of a three-dimensional integrated circuit (3D IC)

a second segment disposed within a second tier of said 3D IC disposed along a second axis horizontally offset from a first axis,

wherein said first segment is electrically connected to said second segment by a first conductive member extending continuously from said first segment to said second segment; and

a second bit line comprising;

a third segment disposed within said first tier of said 3D IC along a third axis parallel to said second axis; and

a fourth segment disposed within said second tier of said 3D IC along a fourth axis parallel to said first axis, wherein said third segment is electrically connected to said fourth segment by a second conductive member extending continuously from said third segment to said fourth segment.

2. The inter-tier memory column of claim 1, wherein said first axis and said second axis are parallel.

3. The inter-tier memory column of claim 1, further comprising an inter-tier word line connected across said first segment and said second segment.

4. The inter-tier memory column of claim 1, comprising:

a first bit line bar comprising;

a first bar segment disposed within said first tier of said 3D IC; and

a second bar segment horizontally offset from said first bar segment.

5. The inter-tier memory column of claim 4, comprising:

a second bit line bar comprising;

a third bar segment disposed within said second tier of said 3D IC; and

a fourth bar segment perpendicular to said third bar segment,

wherein said horizontally offset second bar segment and said perpendicular fourth bar segment are connected by a vertical bit line.

6. The inter-tier memory column of claim 1, further comprising:

a third bit line comprising a fifth segment disposed in said first tier of said 3D IC along a fifth axis and a sixth segment connected to said fifth segment and horizontally offset from said fifth axis; and

a fourth bit line comprising a seventh segment disposed in said second tier of said 3D IC along a seventh axis and an eighth segment connected to said seventh segment and disposed perpendicular to said seventh axis.

7. The inter-tier memory column of claim 6, wherein said third bit line is electrically connected to said fourth bit line by a conductive member extending continuously from said third bit line to said fourth bit line.

8. The inter-tier memory column of claim 1, comprising a first conductive extender coupling said first segment to said second segment.

9. The inter-tier memory column of claim 8, wherein said first coupling extender is disposed perpendicular to said first axis.

10. An inter-tier memory column, comprising:

a first bit line, comprising;

a first segment disposed within a first tier of a three-dimensional integrated circuit (3D IC)

a second segment disposed within a second tier of said 3D IC disposed along a second axis horizontally offset from a first axis;

a first plurality of memory cells electrically connected to said first bit line;

a second bit line comprising;

a third segment disposed within said first tier of said 3D IC along a third axis parallel to said second axis; and

a fourth segment disposed within said second tier of said 3D IC along a fourth axis parallel to said first axis; and

a second plurality of memory cells electrically connected to said second bit line;

wherein said first segment is electrically connected to said second segment by a first conductive member extending continuously from said first segment to said second segment, and wherein said third segment is electrically connected to said fourth segment by a second conductive member extending continuously from said third segment to said fourth segment.

11. The inter-tier memory column of claim 10, wherein said first axis and said second axis are parallel.

12. The inter-tier memory column of claim 10, further comprising an inter-tier word line connected across said first segment and said second segment.

13. The inter-tier memory column of claim 10, comprising:

a first bit line bar comprising;

a first bar segment disposed within said first tier of said 3D IC; and

a second bar segment horizontally offset from said first bar segment; and

a second bit line bar comprising;

a third bar segment disposed within said second tier of said 3D IC; and

a fourth bar segment perpendicular to said third bar segment,

wherein said horizontally offset second bar segment and said perpendicular fourth bar segment are connected by a vertical bit line.

14. The inter-tier memory column of claim 10, further comprising:

a third bit line comprising a fifth segment disposed in said first tier of said 3D IC along a fifth axis and a sixth segment connected to said fifth segment and horizontally offset from said fifth axis; and

a fourth bit line comprising a seventh segment disposed in said second tier of said 3D IC along a seventh axis and an eighth segment connected to said seventh segment and disposed perpendicular to said seventh axis.

15. The inter-tier memory column of claim 14, wherein said third bit line is electrically connected to said fourth bit line by a conductive member extending continuously from said third bit line to said fourth bit line.

16. The inter-tier memory column of claim 10, comprising a first conductive extender coupling said first segment to said second segment, wherein said first coupling extender is disposed perpendicular to said first axis.

17. A method of forming an inter-tier memory column, comprising:

forming a first bit line comprising a first segment disposed within a first tier of a three-dimensional integrated circuit (3D IC) and a second segment disposed within a second tier of said 3D IC disposed along a second axis horizontally offset from a first axis;

forming a second bit line comprising a third segment disposed within said first tier of said 3D IC along a third axis parallel to said second axis and a fourth segment disposed within said second tier of said 3D IC along a fourth axis parallel to said first axis; and

connecting said first segment to said second segment with a first vertical conductive element.

18. The method of claim 17, wherein said first vertical conductive element extends continuously from said first segment to said second segment.

19. The method of claim 17 further comprising:

forming a first bit line bar comprising a first bar segment disposed within said first tier of said 3D IC and a second bar segment horizontally offset from said first bar segment;

forming a second bit line bar comprising a third bar segment disposed within said second tier of said 3D IC and a fourth bar segment perpendicular to said third bar segment; and

connecting said first bit line bar to said second bit line bar with a second vertical conductive element.

20. The method of claim 17, further comprising forming an inter-tier word line which connects the first bit line and the second bit line.