Semiconductor devices and methods of manufacturing the same

• US 10,651,198 B2
• Filed: 04/01/2019
• Issued: 05/12/2020
• Est. Priority Date: 04/04/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Baek, Seok-cheon, Kim, Boh-chang
• Primary Examiner(s): Gumedzoe, Peniel M
• Assistant Examiner(s): Johnson, Christopher A
• Application Number:
  US16/371,444
• Publication Number:
  US 20190312055A1
• Time in Patent Office: 407 Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A semiconductor device includes lower gate electrodes on a substrate in a first direction substantially perpendicular to a top surface of the substrate, upper gate electrodes on the lower gate electrodes in the first direction, and channel structures extending through the lower and upper gate electrodes in the first direction. Each channel structure includes a lower channel structure, an upper channel structure, and a landing pad interconnecting the lower and upper channel structures. The first channel structure includes a first landing pad having a horizontal width substantially greater than that of the lower channel structure of the first channel structure at a first vertical level. The second channel structure located closest to the first channel structure includes a second landing pad having a horizontal width substantially greater than that of the lower channel structure of the second channel structure at a second vertical level lower than the first vertical level.

Claims

1. A semiconductor device, comprising:

a plurality of lower gate electrodes on a substrate in a first direction substantially perpendicular to a top surface of the substrate;

a plurality of upper gate electrodes on the plurality of lower gate electrodes in the first direction, the plurality of upper gate electrodes spaced apart from one another in the first direction; and

a plurality of channel structures, each channel structure of the plurality of channel structures extending through both the plurality of lower gate electrodes and the plurality of upper gate electrodes in the first direction, each channel structure of the plurality of channel structures including

a lower channel structure penetrating through the plurality of lower gate electrodes,

an upper channel structure penetrating through the plurality of upper gate electrodes, and

a landing pad interconnecting the lower channel structure to the upper channel structure,

wherein a first channel structure of the plurality of channel structures includes a first landing pad having a horizontal width substantially greater than a horizontal width of a first lower channel structure of the first channel structure at a first vertical level,

wherein a second channel structure of the plurality of channel structures that is closest to the first channel structure of a remainder of the plurality of channel structures includes a second landing pad having a horizontal width substantially greater than a horizontal width of a second lower channel structure of the second channel structure at a second vertical level,

wherein the first landing pad includes a first lower connection on the first lower channel structure, and a first pad on the first lower connection at the first vertical level, a horizontal width of the first pad being substantially greater than a horizontal width of the first lower connection,

wherein the second landing pad includes a second lower connection on the second lower channel structure, and a second pad on the second lower connection at the second vertical level, a horizontal width of the second pad being substantially greater than a horizontal width of the second lower connection,

wherein the first and second channel structures have a same length in the first direction, the first and second lower channel structures have a same length in the first direction, and the first and second lower connections have different lengths in the first direction, such that the second vertical level is lower than the first vertical level.

2. The semiconductor device of claim 1, wherein

the horizontal width of the first pad is substantially greater than the horizontal width of the first lower channel structure, and

the horizontal width of the second pad is substantially greater than the horizontal width of the second lower channel structure.

3. The semiconductor device of claim 1, wherein a bottom surface of the first pad is located at a level substantially higher than a level of a top surface of the second pad, and the first pad and the second pad are spaced apart from each other in the first direction.

4. The semiconductor device of claim 1, wherein

a bottom surface of a first upper channel structure of the first channel structure contacts the first pad,

a bottom surface of a second upper channel structure of the second channel structure contacts the second pad, and

the bottom surface of the second upper channel structure of the second channel structure is located at a level substantially lower than a level of the bottom surface of the first upper channel structure of the first channel structure.

5. The semiconductor device of claim 1, wherein

the second landing pad further includes an upper connection that is on the second pad and has a horizontal width that is substantially less than the horizontal width of the second pad.

6. The semiconductor device of claim 5, wherein a bottom surface of a second upper channel structure of the second channel structure contacts the upper connection.

7. The semiconductor device of claim 6, wherein a lower portion of the second upper channel structure of the second channel structure surrounds one or more outer surfaces of the upper connection.

8. The semiconductor device of claim 1, wherein

the substrate includes a memory cell region and a peripheral circuit region on at least one side of the memory cell region,

the plurality of lower gate electrodes, the plurality of upper gate electrodes, and the plurality of channel structures are on the memory cell region,

a peripheral circuit element and a peripheral circuit contact structure coupled to the peripheral circuit element are on the peripheral circuit region,

the peripheral circuit contact structure includes a lower contact coupled to the peripheral circuit element, a third landing pad on the lower contact, and an upper contact on the third landing pad, and

a horizontal width of the third landing pad is substantially greater than a horizontal width of the lower contact.

9. The semiconductor device of claim 1, wherein

a first upper channel structure of the first channel structure extends in the first direction,

a first center axis of the first upper channel structure offset from a second center axis of the first lower channel structure of the first channel structure in a second direction that is substantially parallel to the top surface of the substrate, and

substantially an entire bottom surface of the first upper channel structure contacts a top surface of the first pad.

10. The semiconductor device of claim 1, wherein

the substrate includes a peripheral circuit region and a memory cell region, the memory cell region at a level higher than that of the peripheral circuit region from the top surface of the substrate,

the plurality of lower gate electrodes, the plurality of upper gate electrodes, and the plurality of channel structures are on the memory cell region,

a peripheral circuit element is on the peripheral circuit region,

a peripheral circuit contact structure is coupled to the peripheral circuit element,

the peripheral circuit contact structure includes a lower contact coupled to the peripheral circuit element, a fourth landing pad on the lower contact, and an upper contact on the fourth landing pad, and

a horizontal width of the fourth landing pad is substantially greater than a horizontal width of the lower contact.

11. A semiconductor device, comprising:

a plurality of lower gate electrodes on a substrate in a first direction substantially perpendicular to a top surface of the substrate;

a plurality of upper gate electrodes on the plurality of lower gate electrodes in the first direction, the plurality of upper gate electrodes spaced apart from one another in the first direction; and

a plurality of channel structures, each channel structure of the plurality of channel structures extending through both the plurality of lower gate electrodes and the plurality of upper gate electrodes in the first direction, each channel structure of the plurality of channel structures including

a lower channel structure penetrating through the plurality of lower gate electrodes,

an upper channel structure penetrating through the plurality of upper gate electrodes, and

a landing pad interconnecting the lower channel structure to the upper channel structure,

wherein a first channel structure of the plurality of channel structures includes a first landing pad having a largest horizontal width of the first landing pad at a first vertical level,

wherein a second channel structure of the plurality of channel structures that is closest to the first channel structure includes a second landing pad having a largest horizontal width of the second landing pad at a second vertical level,

wherein the first landing pad includes a first lower connection on a first lower channel structure of the first channel structure, and a first pad on the first lower connection at the first vertical level, a horizontal width of the first pad being substantially greater than a horizontal width of the first lower connection and being the largest horizontal width of the first landing pad,

wherein the second landing pad includes a second lower connection on a second lower channel structure of the second channel structure, and a second pad on the second lower connection at the second vertical level, a horizontal width of the second pad being substantially greater than a horizontal width of the second lower connection and being the largest horizontal width of the second landing pad,

wherein the first and second channel structures have a same length in the first direction, the first and second lower channel structures have a same length in the first direction, and the first and second lower connections have different lengths in the first direction, such that the second vertical level is substantially lower than the first vertical level.

12. The semiconductor device of claim 11, wherein

the largest horizontal width of the first landing pad is substantially greater than a horizontal width of a first lower channel structure of the first channel structure, and

the largest horizontal width of the second landing pad is substantially greater than a horizontal width of a second lower channel structure of the second channel structure.

13. The semiconductor device of claim 11, wherein a bottom surface of the first pad is located at a level substantially higher than a level of a top surface of the second pad, and the first pad and the second pad are spaced apart from each other in the first direction.

14. A semiconductor device, comprising:

a plurality of lower gate electrodes on a substrate in a first direction substantially perpendicular to a top surface of the substrate;

a plurality of upper gate electrodes on the plurality of lower gate electrodes in the first direction, the plurality of upper gate electrodes spaced apart from one another in the first direction;

a first channel structure that extends in the first direction and includes a first lower channel structure penetrating through the lower gate electrodes, a first upper channel structure penetrating through the upper gate electrodes, and a first landing pad between the first lower channel structure and the first upper channel structure; and

a second channel structure that extends in the first direction and is spaced apart from the first channel structure in a second direction parallel to the top surface of the substrate and includes a second lower channel structure penetrating through the lower gate electrodes, a second upper channel structure penetrating through the upper gate electrodes, and a second landing pad between the second lower channel structure and the second upper channel structure,

wherein the first and second channel structures have a same length in the first direction, the first and second upper channel structures have different lengths in the first direction, and the first and second lower channel structures have a same length in the first direction, such that a bottom surface of the first upper channel structure contacts the first landing pad at a first vertical level and a bottom surface of the second upper channel structure contacts the second landing pad at a second vertical level substantially lower than the first vertical level.

15. The semiconductor device of claim 14, wherein

the first landing pad includes

a first lower connection coupled to the first lower channel structure;

and

a first pad contacting the bottom surface of the first upper channel structure on the first lower connection, and

the second landing pad further includes

a second lower connection coupled to the second lower channel structure; and

a second pad contacting the bottom surface of the second upper channel structure on the second lower connection, and

a horizontal width of the first pad is substantially greater than a horizontal width of the first lower channel structure and a horizontal width of the second pad is substantially greater than a horizontal width of the second lower channel structure.

16. The semiconductor device of claim 15, wherein

the first upper channel structure vertically overlaps with the first pad, and

the first upper channel structure vertically overlaps with at least a portion of the first lower channel structure.

17. The semiconductor device of claim 14, wherein the first upper channel structure extends in the first direction and a first center axis of the first upper channel structure is offset from a second center axis of the first lower channel structure in the second direction.

18. The semiconductor device of claim 14, further comprising:

an interlayer insulating film between the plurality of lower gate electrodes and the plurality of upper gate electrodes,

wherein a side surface of the first landing pad and a side surface of the second landing pad are surrounded by the interlayer insulating film.